Make clippy happy, again.

6 files changed, 7 insertions, 9 deletions

diff --git a/src/lib.rs b/src/lib.rs
index 706d02f..b4e1c96 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -33,6 +33,7 @@
 #![deny(missing_docs)]
 #![no_std]
 #![allow(clippy::identity_op)]
+#![allow(clippy::missing_safety_doc)]
 
 extern crate aligned;
 extern crate bare_metal;
diff --git a/src/macros.rs b/src/macros.rs
index 6b3b269..b578370 100644
--- a/src/macros.rs
+++ b/src/macros.rs
@@ -78,8 +78,6 @@ macro_rules! singleton {
 /// ``` compile_fail
 /// use cortex_m::singleton;
 ///
-/// fn main() {}
-///
 /// fn foo() {
 ///     // check that the call to `uninitialized` requires unsafe
 ///     singleton!(: u8 = std::mem::uninitialized());
@@ -92,8 +90,6 @@ const CFAIL: () = ();
 /// #![deny(unsafe_code)]
 /// use cortex_m::singleton;
 ///
-/// fn main() {}
-///
 /// fn foo() {
 ///     // check that calls to `singleton!` don't trip the `unsafe_code` lint
 ///     singleton!(: u8 = 0);
diff --git a/src/peripheral/dwt.rs b/src/peripheral/dwt.rs
index 1f7655a..bd7b3ff 100644
--- a/src/peripheral/dwt.rs
+++ b/src/peripheral/dwt.rs
@@ -82,6 +82,6 @@ impl DWT {
     #[cfg(not(armv6m))]
     pub fn unlock() {
         // NOTE(unsafe) atomic write to a stateless, write-only register
-        unsafe { (*Self::ptr()).lar.write(0xC5ACCE55) }
+        unsafe { (*Self::ptr()).lar.write(0xC5AC_CE55) }
     }
 }
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index 7019224..9432dea 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -1,3 +1,4 @@
+#![allow(clippy::needless_doctest_main)]
 //! Core peripherals
 //!
 //! # API
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs
index 4ea3b7a..fcee080 100644
--- a/src/peripheral/nvic.rs
+++ b/src/peripheral/nvic.rs
@@ -164,7 +164,7 @@ impl NVIC {
         {
             // NOTE(unsafe) atomic read with no side effects
             let ipr_n = unsafe { (*Self::ptr()).ipr[Self::ipr_index(&interrupt)].read() };
-            let prio = (ipr_n >> Self::ipr_shift(&interrupt)) & 0x000000ff;
+            let prio = (ipr_n >> Self::ipr_shift(&interrupt)) & 0x0000_00ff;
             prio as u8
         }
     }
@@ -251,7 +251,7 @@ impl NVIC {
         #[cfg(armv6m)]
         {
             self.ipr[Self::ipr_index(&interrupt)].modify(|value| {
-                let mask = 0x000000ff << Self::ipr_shift(&interrupt);
+                let mask = 0x0000_00ff << Self::ipr_shift(&interrupt);
                 let prio = u32::from(prio) << Self::ipr_shift(&interrupt);
 
                 (value & !mask) | prio
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index 98434e5..1f37a43 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -781,7 +781,7 @@ impl SCB {
         {
             // NOTE(unsafe) atomic read with no side effects
             let shpr = unsafe { (*Self::ptr()).shpr[usize::from((index - 8) / 4)].read() };
-            let prio = (shpr >> (8 * (index % 4))) & 0x000000ff;
+            let prio = (shpr >> (8 * (index % 4))) & 0x0000_00ff;
             prio as u8
         }
     }
@@ -810,7 +810,7 @@ impl SCB {
         {
             self.shpr[usize::from((index - 8) / 4)].modify(|value| {
                 let shift = 8 * (index % 4);
-                let mask = 0x000000ff << shift;
+                let mask = 0x0000_00ff << shift;
                 let prio = u32::from(prio) << shift;
 
                 (value & !mask) | prio