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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2020-08-27 19:08:51 +0000 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2020-08-27 19:08:51 +0000 |
| commit | bbf4a54a69631653c2bd1b66ce910b6869f240ec (patch) | |
| tree | 78b5a11822729ccd3a99d226fa06c8e8a5432a4f | |
| parent | 13e04bd4c4750c27772dcdb7154e38b9b7776826 (diff) | |
| parent | 0138f274cfeaaf2572224fa8a5278f6e793ba0a8 (diff) | |
| download | cortex-m-bbf4a54a69631653c2bd1b66ce910b6869f240ec.tar.gz cortex-m-bbf4a54a69631653c2bd1b66ce910b6869f240ec.tar.zst cortex-m-bbf4a54a69631653c2bd1b66ce910b6869f240ec.zip | |
Merge #260
260: Remove outdated TODO r=therealprof a=jonas-schievink
STIR has been wrapped in the NVIC (it isn't standalone)
Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
| -rw-r--r-- | src/peripheral/mod.rs | 2 | ||||
| -rw-r--r-- | src/peripheral/nvic.rs | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index cae1133..961f31d 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -55,8 +55,6 @@ //! //! - ARMv7-M Architecture Reference Manual (Issue E.b) - Chapter B3 -// TODO stand-alone register: STIR - use core::marker::PhantomData; use core::ops; diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index a2f85f4..4332707 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -79,9 +79,11 @@ impl NVIC { /// /// Writing a value to the INTID field is the same as manually pending an interrupt by setting /// the corresponding interrupt bit in an Interrupt Set Pending Register. This is similar to - /// `set_pending`. + /// [`NVIC::pend`]. /// /// This method is not available on ARMv6-M chips. + /// + /// [`NVIC::pend`]: #method.pend #[cfg(not(armv6m))] #[inline] pub fn request<I>(&mut self, interrupt: I) |