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| author |  Dario Nieuwenhuis <dirbaio@dirbaio.net>
| 2023-02-26 23:43:12 +0100 |
|---|---|---|
| committer | Dario Nieuwenhuis <dirbaio@dirbaio.net>
| 2023-02-27 00:07:24 +0100 |
| commit | d6086d3f075be0060ffc3fd0559bcf662dc09a98 (patch) | |
| tree | 40144c41f30e4c267837283e588db9b2ff65cfad | |
| parent | 88c6f8637f4eccbb44f57be5bc10bcfc88fbb3c8 (diff) | |
| download | cortex-m-d6086d3f075be0060ffc3fd0559bcf662dc09a98.tar.gz cortex-m-d6086d3f075be0060ffc3fd0559bcf662dc09a98.tar.zst cortex-m-d6086d3f075be0060ffc3fd0559bcf662dc09a98.zip | |
nvic: do not require `&mut self` for `request`.
| -rw-r--r-- | CHANGELOG.md | 4 | ||||
| -rw-r--r-- | src/peripheral/nvic.rs | 7 |
2 files changed, 7 insertions, 4 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index ebcd2c4..db2827f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Breaking changes + +- `NVIC::request()` no longer requires `&mut self`. + ### Added - Updated `SCB.ICSR.VECTACTIVE`/`SCB::vect_active()` to be 9 bits instead of 8. Also fixes `VectActive::from` to take a `u16` and subtract `16` for diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index 067c1d9..fccd6a2 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -94,15 +94,14 @@ impl NVIC { /// [`NVIC::pend`]: #method.pend #[cfg(not(armv6m))] #[inline] - pub fn request<I>(&mut self, interrupt: I) + pub fn request<I>(interrupt: I) where I: InterruptNumber, { let nr = interrupt.number(); - unsafe { - self.stir.write(u32::from(nr)); - } + // NOTE(ptr) this is a write to a stateless register + unsafe { (*Self::PTR).stir.write(u32::from(nr)) } } /// Disables `interrupt` |