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| author |  Michael Watzko <michael@watzko.de>
| 2018-09-06 00:27:39 +0200 |
|---|---|---|
| committer | Michael Watzko <michael@watzko.de>
| 2018-09-06 00:27:39 +0200 |
| commit | da13bee359d31185a489762acc487f3245fd2673 (patch) | |
| tree | 0f05dbbff7855194d1e80dc021ca5918a4f6ceeb | |
| parent | 385b3eb5b9f4f37503270fb3e9d7252a49d14c1b (diff) | |
| download | cortex-m-da13bee359d31185a489762acc487f3245fd2673.tar.gz cortex-m-da13bee359d31185a489762acc487f3245fd2673.tar.zst cortex-m-da13bee359d31185a489762acc487f3245fd2673.zip | |
Rename BIT_TRCENA to DCB_DEMCR_TRCENA, replace 0x01 with 1
| -rw-r--r-- | src/peripheral/dcb.rs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index 363747c..14dc75b 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -4,7 +4,7 @@ use volatile_register::{RW, WO}; use peripheral::DCB; -const BIT_TRCENA: u32 = 0x01 << 24; +const DCB_DEMCR_TRCENA: u32 = 1 << 24; /// Register block #[repr(C)] @@ -26,12 +26,12 @@ impl DCB { /// soft-reset, only on power reset. pub fn enable_trace(&mut self) { // set bit 24 / TRCENA - unsafe { self.demcr.modify(|w| w | BIT_TRCENA); } + unsafe { self.demcr.modify(|w| w | DCB_DEMCR_TRCENA); } } /// Disables TRACE. See `DCB::enable_trace()` for more details pub fn disable_trace(&mut self) { // unset bit 24 / TRCENA - unsafe { self.demcr.modify(|w| w & !BIT_TRCENA); } + unsafe { self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA); } } } |