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author | 2018-11-20 20:47:50 +0000 | |
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committer | 2018-11-20 20:47:50 +0000 | |
commit | db6718650505d09fc9a959fe0ffa4b41d2fc1d4b (patch) | |
tree | 6236cdba557d3ecd57b5deeb33ab5a8c9051a841 | |
parent | b70a2179f4e8ee7908b61a6a97970e0cfcf2f313 (diff) | |
parent | f7f2555025b1cb0809396d242315d881defa1dde (diff) | |
download | cortex-m-db6718650505d09fc9a959fe0ffa4b41d2fc1d4b.tar.gz cortex-m-db6718650505d09fc9a959fe0ffa4b41d2fc1d4b.tar.zst cortex-m-db6718650505d09fc9a959fe0ffa4b41d2fc1d4b.zip |
Merge #124
124: Add api to set SLEEPONEXIT bit in SCR register r=korken89 a=simonvandel
Co-authored-by: Simon Vandel Sillesen <simon.vandel@gmail.com>
-rw-r--r-- | src/peripheral/scb.rs | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 888a3db..4bf9270 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -596,6 +596,24 @@ impl SCB { } } +const SCB_SCR_SLEEPONEXIT: u32 = 0x1 << 1; + +impl SCB { + /// Set the SLEEPONEXIT bit in the SCR register + pub fn set_sleeponexit(&mut self) { + unsafe { + self.scr.modify(|scr| scr | SCB_SCR_SLEEPONEXIT); + } + } + + /// Clear the SLEEPONEXIT bit in the SCR register + pub fn clear_sleeponexit(&mut self) { + unsafe { + self.scr.modify(|scr| scr & !SCB_SCR_SLEEPONEXIT); + } + } +} + const SCB_AIRCR_VECTKEY: u32 = 0x05FA << 16; const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x5 << 8; const SCB_AIRCR_SYSRESETREQ: u32 = 1 << 2; |