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| author |  Michael Watzko <michael@watzko.de>
| 2018-09-05 23:46:10 +0200 |
|---|---|---|
| committer | Michael Watzko <michael@watzko.de>
| 2018-09-05 23:46:10 +0200 |
| commit | e6f511ade92b19c152d74d7ba6df2034dfd61bbe (patch) | |
| tree | b0c4175ee583aca55e31899bbef249777a61ae16 | |
| parent | 49a6daed832d0e25fd1d4fc828b3c804eb684c22 (diff) | |
| download | cortex-m-e6f511ade92b19c152d74d7ba6df2034dfd61bbe.tar.gz cortex-m-e6f511ade92b19c152d74d7ba6df2034dfd61bbe.tar.zst cortex-m-e6f511ade92b19c152d74d7ba6df2034dfd61bbe.zip | |
Move the whole shift to the constant
| -rw-r--r-- | src/peripheral/dcb.rs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index fe73002..94f7d96 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -4,7 +4,7 @@ use volatile_register::{RW, WO}; use peripheral::DCB; -const BIT_TRACENA: u8 = 24; +const BIT_TRACENA: u32 = 0x01 << 24; /// Register block #[repr(C)] @@ -26,12 +26,12 @@ impl DCB { /// soft-reset, only on power reset. pub fn enable_trace(&mut self) { // set bit 24 / TRACENA - unsafe { self.demcr.modify(|w| w | (0x01 << BIT_TRACENA)); } + unsafe { self.demcr.modify(|w| w | BIT_TRACENA); } } /// Disables TRACE. See `DCB::enable_trace()` for more details pub fn disable_trace(&mut self) { // unset bit 24 / TRACENA - unsafe { self.demcr.modify(|w| w & !(0x01 << BIT_TRACENA)); } + unsafe { self.demcr.modify(|w| w & !BIT_TRACENA); } } } |