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authorGravatar Viktor Sonesten <v@tmplt.dev> 2021-04-28 18:46:39 +0200
committerGravatar Viktor Sonesten <v@tmplt.dev> 2021-04-28 18:47:08 +0200
commitf75f17f764bded9a75475683ac12a55ed1925d67 (patch)
treea5027dc769cca0987c935d02ee5c67d37442a89d
parent720282fb8ee406a14c56f67ed1595c24133f7e5d (diff)
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dwt: impl functions related to trace generation
-rw-r--r--src/peripheral/dwt.rs28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/peripheral/dwt.rs b/src/peripheral/dwt.rs
index 043223a..4684f75 100644
--- a/src/peripheral/dwt.rs
+++ b/src/peripheral/dwt.rs
@@ -70,6 +70,34 @@ impl DWT {
unsafe { self.ctrl.modify(|r| r | 1) }
}
+ /// Whether to enable exception tracing
+ // TODO find out if this is supported om armv6m
+ #[inline]
+ pub fn enable_exception_tracing(&mut self, bit: bool) {
+ unsafe {
+ // EXCTRCENA
+ if bit {
+ self.ctrl.modify(|r| r | (1 << 16));
+ } else {
+ self.ctrl.modify(|r| r & !(1 << 16));
+ }
+ }
+ }
+
+ /// Whether to periodically generate PC samples
+ // TODO find out if this is supported on armv6m
+ #[inline]
+ pub fn enable_pc_samples(&mut self, bit: bool) {
+ unsafe {
+ // PCSAMPLENA
+ if bit {
+ self.ctrl.modify(|r| r | (1 << 12));
+ } else {
+ self.ctrl.modify(|r| r & !(1 << 12));
+ }
+ }
+ }
+
/// Returns the current clock cycle count
#[cfg(not(armv6m))]
#[inline]