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authorGravatar bors[bot] <26634292+bors[bot]@users.noreply.github.com> 2020-10-02 16:44:57 +0000
committerGravatar GitHub <noreply@github.com> 2020-10-02 16:44:57 +0000
commitf77d64a2d1505335e4a170d03a40993bb066fd02 (patch)
tree06c7b191bc4d92137762ba88a8aa072426d36bda /asm
parent43b9383cbedc5b0fb0b2df51df0e7af742fb7b61 (diff)
parent7102bd4c048d96f65f79f32c1f0b1c59e1a32a51 (diff)
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Merge #268
268: Add some Armv8-M assembly routines r=jonas-schievink a=hug-dev Adds access to `MSP_NS` and the `BXNS` instruction. Also adds `__dsb` which was missing. Executed `cargo xtask assemble` and pushed everything, I hope that's enough. Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
Diffstat (limited to 'asm')
-rw-r--r--asm/inline.rs17
-rw-r--r--asm/lib.rs4
2 files changed, 21 insertions, 0 deletions
diff --git a/asm/inline.rs b/asm/inline.rs
index 3fbba92..9a0c66e 100644
--- a/asm/inline.rs
+++ b/asm/inline.rs
@@ -308,6 +308,23 @@ mod v8m {
asm!("ttat {target}, {target}", target = inout(reg) target);
target
}
+
+ #[inline(always)]
+ pub unsafe fn __msp_ns_r() -> u32 {
+ let r;
+ asm!("mrs {}, MSP_NS", out(reg) r);
+ r
+ }
+
+ #[inline(always)]
+ pub unsafe fn __msp_ns_w(val: u32) {
+ asm!("msr MSP_NS, {}", in(reg) val);
+ }
+
+ #[inline(always)]
+ pub unsafe fn __bxns(val: u32) {
+ asm!("BXNS {}", in(reg) val);
+ }
}
#[cfg(armv8m_main)]
diff --git a/asm/lib.rs b/asm/lib.rs
index 50e1db6..93d56fb 100644
--- a/asm/lib.rs
+++ b/asm/lib.rs
@@ -60,6 +60,7 @@ shims! {
fn __cpsie();
fn __delay(cyc: u32);
fn __dmb();
+ fn __dsb();
fn __isb();
fn __msp_r() -> u32;
fn __msp_w(val: u32);
@@ -97,6 +98,9 @@ shims! {
fn __ttt(target: u32) -> u32;
fn __tta(target: u32) -> u32;
fn __ttat(target: u32) -> u32;
+ fn __msp_ns_r() -> u32;
+ fn __msp_ns_w(val: u32);
+ fn __bxns(val: u32);
}
// Mainline only.