aboutsummaryrefslogtreecommitdiff
path: root/cortex-m-rt/src
diff options
context:
space:
mode:
authorGravatar Emil Fresk <emil.fresk@gmail.com> 2020-03-30 10:02:16 +0200
committerGravatar Emil Fresk <emil.fresk@gmail.com> 2020-03-30 10:02:16 +0200
commitffffb7b3aaef1d9bb4e4b81347ed8f1d50e50ea4 (patch)
tree57f3d5e746803e85276e9d831a26628507607c89 /cortex-m-rt/src
parentaa68192064c8acd662020264957eda8746f709f6 (diff)
downloadcortex-m-ffffb7b3aaef1d9bb4e4b81347ed8f1d50e50ea4.tar.gz
cortex-m-ffffb7b3aaef1d9bb4e4b81347ed8f1d50e50ea4.tar.zst
cortex-m-ffffb7b3aaef1d9bb4e4b81347ed8f1d50e50ea4.zip
Changed Hardfault's and DefaultHander's default implementations to panic
Diffstat (limited to 'cortex-m-rt/src')
-rw-r--r--cortex-m-rt/src/lib.rs22
1 files changed, 9 insertions, 13 deletions
diff --git a/cortex-m-rt/src/lib.rs b/cortex-m-rt/src/lib.rs
index 0d62d47..06e945d 100644
--- a/cortex-m-rt/src/lib.rs
+++ b/cortex-m-rt/src/lib.rs
@@ -199,14 +199,15 @@
//! won't find it.
//!
//! - `DefaultHandler`. This is the default handler. If not overridden using `#[exception] fn
-//! DefaultHandler(..` this will be an infinite loop.
+//! DefaultHandler(..` this will cause a panic with the message "DefaultHandler #`i`", where `i` is
+//! the number of the interrupt handler.
//!
//! - `HardFaultTrampoline`. This is the real hard fault handler. This function is simply a
//! trampoline that jumps into the user defined hard fault handler named `HardFault`. The
//! trampoline is required to set up the pointer to the stacked exception frame.
//!
//! - `HardFault`. This is the user defined hard fault handler. If not overridden using
-//! `#[exception] fn HardFault(..` it will default to an infinite loop.
+//! `#[exception] fn HardFault(..` it will default to a panic with message "Hardfault".
//!
//! - `__STACK_START`. This is the first entry in the `.vector_table` section. This symbol contains
//! the initial value of the stack pointer; this is where the stack will be located -- the stack
@@ -402,7 +403,6 @@ extern crate cortex_m_rt_macros as macros;
extern crate r0;
use core::fmt;
-use core::sync::atomic::{self, Ordering};
/// Attribute to declare an interrupt (AKA device-specific exception) handler
///
@@ -945,21 +945,17 @@ pub unsafe extern "C" fn Reset() -> ! {
#[link_section = ".HardFault.default"]
#[no_mangle]
pub unsafe extern "C" fn HardFault_(ef: &ExceptionFrame) -> ! {
- loop {
- // add some side effect to prevent this from turning into a UDF instruction
- // see rust-lang/rust#28728 for details
- atomic::compiler_fence(Ordering::SeqCst);
- }
+ panic!("Hardfault");
}
#[doc(hidden)]
#[no_mangle]
pub unsafe extern "C" fn DefaultHandler_() -> ! {
- loop {
- // add some side effect to prevent this from turning into a UDF instruction
- // see rust-lang/rust#28728 for details
- atomic::compiler_fence(Ordering::SeqCst);
- }
+ const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32;
+
+ let irqn = core::ptr::read(SCB_ICSR) as u8 as i16 - 16;
+
+ panic!("DefaultHandler #{}", irqn);
}
#[doc(hidden)]