Merge #279

279: Add barriers after FPU enabling r=adamgreig a=thalesfragoso

This only seems to be required for M7 cores, but since we can't know the specific core, we can't filter on that.

I thought about using the SCB's `RegisterBlock` from cortex-m to enable the FPU, but the [registers](https://docs.rs/cortex-m/0.6.2/cortex_m/peripheral/scb/struct.RegisterBlock.html) are just the generics `RW` which isn't that different from what we're doing right now, and we would need `Peripherals::steal` to use the methods from SCB which would set the `CORE_PERIPHERALS`/`TAKEN` flag.

And one question, with this change, can we get rid of the `trampoline()` function? I don't think the compiler will do reordering across foreign functions calls (dsb/isb), but I might be missing something.

Co-authored-by: Thales Fragoso <thales.fragosoz@gmail.com>

2 files changed, 5 insertions, 2 deletions

diff --git a/cortex-m-rt/Cargo.toml b/cortex-m-rt/Cargo.toml
index f8f8342..1a62ab6 100644
--- a/cortex-m-rt/Cargo.toml
+++ b/cortex-m-rt/Cargo.toml
@@ -19,9 +19,9 @@ links = "cortex-m-rt" # Prevent multiple versions of cortex-m-rt being linked
 [dependencies]
 r0 = "1.0"
 cortex-m-rt-macros = { path = "macros", version = "=0.6.11" }
+cortex-m = "0.6"
 
 [dev-dependencies]
-cortex-m = "0.6"
 panic-halt = "0.2.0"
 cortex-m-semihosting = "0.3"
 
diff --git a/cortex-m-rt/src/lib.rs b/cortex-m-rt/src/lib.rs
index ba50572..47bc1f7 100644
--- a/cortex-m-rt/src/lib.rs
+++ b/cortex-m-rt/src/lib.rs
@@ -916,12 +916,12 @@ pub unsafe extern "C" fn Reset() -> ! {
     r0::zero_bss(&mut __sbss, &mut __ebss);
     r0::init_data(&mut __sdata, &mut __edata, &__sidata);
 
+    #[allow(clippy::match_single_binding)]
     match () {
         #[cfg(not(has_fpu))]
         () => main(),
         #[cfg(has_fpu)]
         () => {
-            // We redefine these here to avoid pulling the `cortex-m` crate as a dependency
             const SCB_CPACR: *mut u32 = 0xE000_ED88 as *mut u32;
             const SCB_CPACR_FPU_ENABLE: u32 = 0b01_01 << 20;
             const SCB_CPACR_FPU_USER: u32 = 0b10_10 << 20;
@@ -932,6 +932,9 @@ pub unsafe extern "C" fn Reset() -> ! {
                 *SCB_CPACR | SCB_CPACR_FPU_ENABLE | SCB_CPACR_FPU_USER,
             );
 
+            cortex_m::asm::dsb();
+            cortex_m::asm::isb();
+
             // this is used to prevent the compiler from inlining the user `main` into the reset
             // handler. Inlining can cause the FPU instructions in the user `main` to be executed
             // before enabling the FPU, and that would produce a hard to diagnose hard fault at