[ARMv6-M] initialize the LR register

the ARMv6-M Architecture Reference Manual (ARM DDI 0419D) indicates in section
B1.5.5 "Reset behavior" that the LR (Link Register) starts in an unknown state
when the Reset handler is taken and that its "Value must be initialised by
software"

So this PR does that: it initializes the LR register to 0xFFFF_FFFF (-1) first
thing in the Reset handler (only for v6). The manual doesn't say which value to
use so I decided to use the value used by the ARMv7-M (v7 sets LR to 0xFFFF_FFFF
before invoking the Reset handler; see its Architecture Manual for details).

The values of LR (these are pushed onto the stack in function preludes) are used
to unwind the stack (e.g. GDB's `backtrace` or a future `cortex_m_panic_unwind`
handler). Having the initial stack frame use a known value on all Cortex-M
variants makes it easier to implement `panic_unwind` and avoids virtual
unwinders like GDB `backtrace` trying to unwind beyond the `Reset` handler

Note that this implementation uses a trampoline that runs before `Reset` to set
LR on v6. This is required because the prelude of the `Reset` routine will push
LR onto the stack; we want that LR value to be -1. Calling `register::lr::write`
from `Reset` would perform the write after LR has been pushed onto the stack and
that's too late

10 files changed, 29 insertions, 0 deletions

diff --git a/cortex-m-rt/asm.s b/cortex-m-rt/asm.s
index 1be4a02..37dedbd 100644
--- a/cortex-m-rt/asm.s
+++ b/cortex-m-rt/asm.s
@@ -40,3 +40,17 @@ FpuTrampoline:
   # Hand execution over to `main`.
   bl main
   # Note: `main` must not return. `bl` is used only because it has a wider range than `b`.
+
+  # ARMv6-M leaves LR in an unknown state on Reset
+  # this trampoline sets LR before it's pushed onto the stack by Reset
+  .section .PreResetTrampoline, "ax"
+  .global PreResetTrampoline
+  # .type and .thumb_func are both required; otherwise its Thumb bit does not
+  # get set and an invalid vector table is generated
+  .type PreResetTrampoline,%function
+  .thumb_func
+PreResetTrampoline:
+  # set LR to the initial value used by the ARMv7-M (0xFFFF_FFFF)
+  ldr r0,=0xffffffff
+  mov lr,r0
+  b Reset
diff --git a/cortex-m-rt/bin/thumbv6m-none-eabi.a b/cortex-m-rt/bin/thumbv6m-none-eabi.a
index 99f1b1a..65684da 100644
--- a/cortex-m-rt/bin/thumbv6m-none-eabi.a
+++ b/cortex-m-rt/bin/thumbv6m-none-eabi.a
diff --git a/cortex-m-rt/bin/thumbv7em-none-eabi.a b/cortex-m-rt/bin/thumbv7em-none-eabi.a
index 020b796..c4e1f47 100644
--- a/cortex-m-rt/bin/thumbv7em-none-eabi.a
+++ b/cortex-m-rt/bin/thumbv7em-none-eabi.a
diff --git a/cortex-m-rt/bin/thumbv7em-none-eabihf.a b/cortex-m-rt/bin/thumbv7em-none-eabihf.a
index 020b796..c4e1f47 100644
--- a/cortex-m-rt/bin/thumbv7em-none-eabihf.a
+++ b/cortex-m-rt/bin/thumbv7em-none-eabihf.a
diff --git a/cortex-m-rt/bin/thumbv7m-none-eabi.a b/cortex-m-rt/bin/thumbv7m-none-eabi.a
index 16ade10..ed96942 100644
--- a/cortex-m-rt/bin/thumbv7m-none-eabi.a
+++ b/cortex-m-rt/bin/thumbv7m-none-eabi.a
diff --git a/cortex-m-rt/bin/thumbv8m.base-none-eabi.a b/cortex-m-rt/bin/thumbv8m.base-none-eabi.a
index 264b029..f1c7734 100644
--- a/cortex-m-rt/bin/thumbv8m.base-none-eabi.a
+++ b/cortex-m-rt/bin/thumbv8m.base-none-eabi.a
diff --git a/cortex-m-rt/bin/thumbv8m.main-none-eabi.a b/cortex-m-rt/bin/thumbv8m.main-none-eabi.a
index 01b343f..cb216dc 100644
--- a/cortex-m-rt/bin/thumbv8m.main-none-eabi.a
+++ b/cortex-m-rt/bin/thumbv8m.main-none-eabi.a
diff --git a/cortex-m-rt/bin/thumbv8m.main-none-eabihf.a b/cortex-m-rt/bin/thumbv8m.main-none-eabihf.a
index 01b343f..cb216dc 100644
--- a/cortex-m-rt/bin/thumbv8m.main-none-eabihf.a
+++ b/cortex-m-rt/bin/thumbv8m.main-none-eabihf.a
diff --git a/cortex-m-rt/link.x.in b/cortex-m-rt/link.x.in
index f5e582e..f4f4959 100644
--- a/cortex-m-rt/link.x.in
+++ b/cortex-m-rt/link.x.in
@@ -85,6 +85,10 @@ SECTIONS
   /* ### .text */
   .text _stext :
   {
+    /* place these 2 close to each other or the `b` instruction will fail to link */
+    *(.PreResetTrampoline);
+    *(.Reset);
+
     *(.text .text.*);
     *(.HardFaultTrampoline);
     *(.HardFault.*);
diff --git a/cortex-m-rt/src/lib.rs b/cortex-m-rt/src/lib.rs
index e2dd667..ab4bc3f 100644
--- a/cortex-m-rt/src/lib.rs
+++ b/cortex-m-rt/src/lib.rs
@@ -923,9 +923,17 @@ pub fn heap_start() -> *mut u32 {
 #[doc(hidden)]
 #[link_section = ".vector_table.reset_vector"]
 #[no_mangle]
+#[cfg(not(armv6m))]
 pub static __RESET_VECTOR: unsafe extern "C" fn() -> ! = Reset;
 
 #[doc(hidden)]
+#[link_section = ".vector_table.reset_vector"]
+#[no_mangle]
+#[cfg(armv6m)]
+pub static __RESET_VECTOR: unsafe extern "C" fn() -> ! = PreResetTrampoline;
+
+#[doc(hidden)]
+#[link_section = ".Reset"]
 #[no_mangle]
 pub unsafe extern "C" fn Reset() -> ! {
     extern "C" {
@@ -1030,6 +1038,9 @@ pub enum Exception {
 pub use self::Exception as exception;
 
 extern "C" {
+    #[cfg(armv6m)]
+    fn PreResetTrampoline() -> !;
+
     fn NonMaskableInt();
 
     fn HardFaultTrampoline();