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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2020-02-05 00:10:18 +0000 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2020-02-05 00:10:18 +0000 |
| commit | 319773eaf338cbf7d1380611ba62f5a1dbfa3094 (patch) | |
| tree | 98185a32b9458ced09ed10a0a985bcb37d677c6c /src/asm.rs | |
| parent | 22d47dd75e9fb5004e0192666123d28f0a418310 (diff) | |
| parent | 9ad4e10d8a96b283b31b3309a65678513d50e270 (diff) | |
| download | cortex-m-319773eaf338cbf7d1380611ba62f5a1dbfa3094.tar.gz cortex-m-319773eaf338cbf7d1380611ba62f5a1dbfa3094.tar.zst cortex-m-319773eaf338cbf7d1380611ba62f5a1dbfa3094.zip | |
Merge #192
192: Update and improve cache operations. r=jonas-schievink a=adamgreig
Closes #47, #188.
I've implemented the proposed methods from #47 and marked all d-cache invalidation functions as unsafe. It's not unsafe to invalidate i-cache or branch predictor as they are read-only caches. The clean and clean+invalidate operations do not alter memory from the executing core's point of view so are also safe.
It wasn't possible to remove the requirement to pass in `&mut CPUID` as you require synchronized access to `CPUID` to read the number of sets and ways in the cache, which is required to fully clean or invalidate them, which is required to enable or disable them. So it goes.
Breaking change due to changing safety of d-cache invalidation functions.
Co-authored-by: Adam Greig <adam@adamgreig.com>
Diffstat (limited to 'src/asm.rs')
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