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author | 2017-12-23 17:51:13 +0000 | |
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committer | 2017-12-23 17:51:13 +0000 | |
commit | bdc7ca96c5593e410c8f49025d2b0fced7607a4d (patch) | |
tree | eafb76c2e0eee5492e18ac931e28c50b1be13a7a /src/asm.rs | |
parent | 9a80bae79d1eb9111e50406cb7cc088246deb04d (diff) | |
parent | f79f4b73fb19ad537669d71f3f567aad9810a8f5 (diff) | |
download | cortex-m-bdc7ca96c5593e410c8f49025d2b0fced7607a4d.tar.gz cortex-m-bdc7ca96c5593e410c8f49025d2b0fced7607a4d.tar.zst cortex-m-bdc7ca96c5593e410c8f49025d2b0fced7607a4d.zip |
Auto merge of #71 - japaric:unimplemented-asm, r=japaric
map asm! ops to unimplemented! on non ARM targets
closes #63
cc @hannobraun
Diffstat (limited to 'src/asm.rs')
-rw-r--r-- | src/asm.rs | 73 |
1 files changed, 26 insertions, 47 deletions
@@ -7,58 +7,43 @@ /// cause an exception #[inline(always)] pub fn bkpt() { - #[cfg(target_arch = "arm")] - unsafe { - asm!("bkpt" - : - : - : - : "volatile"); + match () { + #[cfg(target_arch = "arm")] + () => unsafe { asm!("bkpt" :::: "volatile") }, + #[cfg(not(target_arch = "arm"))] + () => unimplemented!(), } } /// A no-operation. Useful to prevent delay loops from being optimized away. -#[inline(always)] +#[inline] pub fn nop() { - unsafe { - asm!("nop" - : - : - : - : "volatile"); + match () { + #[cfg(target_arch = "arm")] + () => unsafe { asm!("nop" :::: "volatile") }, + #[cfg(not(target_arch = "arm"))] + () => unimplemented!(), } } /// Wait For Event -#[inline(always)] +#[inline] pub fn wfe() { match () { #[cfg(target_arch = "arm")] - () => unsafe { - asm!("wfe" - : - : - : - : "volatile") - }, + () => unsafe { asm!("wfe" :::: "volatile") }, #[cfg(not(target_arch = "arm"))] - () => {} + () => unimplemented!(), } } /// Wait For Interrupt -#[inline(always)] +#[inline] pub fn wfi() { match () { #[cfg(target_arch = "arm")] - () => unsafe{ - asm!("wfi" - : - : - : - : "volatile") - }, + () => unsafe { asm!("wfi" :::: "volatile") }, #[cfg(not(target_arch = "arm"))] - () => {} + () => unimplemented!(), } } @@ -66,15 +51,13 @@ pub fn wfi() { /// /// Flushes the pipeline in the processor, so that all instructions following the `ISB` are fetched /// from cache or memory, after the instruction has been completed. -#[inline(always)] +#[inline] pub fn isb() { match () { #[cfg(target_arch = "arm")] - () => unsafe { - asm!("isb 0xF" : : : "memory" : "volatile"); - }, + () => unsafe { asm!("isb 0xF" : : : "memory" : "volatile") }, #[cfg(not(target_arch = "arm"))] - () => {} + () => unimplemented!(), } } @@ -86,15 +69,13 @@ pub fn isb() { /// /// * any explicit memory access made before this instruction is complete /// * all cache and branch predictor maintenance operations before this instruction complete -#[inline(always)] +#[inline] pub fn dsb() { match () { #[cfg(target_arch = "arm")] - () => unsafe { - asm!("dsb 0xF" : : : "memory" : "volatile"); - }, + () => unsafe { asm!("dsb 0xF" : : : "memory" : "volatile") }, #[cfg(not(target_arch = "arm"))] - () => {} + () => unimplemented!(), } } @@ -103,14 +84,12 @@ pub fn dsb() { /// Ensures that all explicit memory accesses that appear in program order before the `DMB` /// instruction are observed before any explicit memory accesses that appear in program order /// after the `DMB` instruction. -#[inline(always)] +#[inline] pub fn dmb() { match () { #[cfg(target_arch = "arm")] - () => unsafe { - asm!("dmb 0xF" : : : "memory" : "volatile"); - }, + () => unsafe { asm!("dmb 0xF" : : : "memory" : "volatile") }, #[cfg(not(target_arch = "arm"))] - () => {} + () => unimplemented!(), } } |