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authorGravatar Jorge Aparicio <japaricious@gmail.com> 2017-03-11 23:15:39 -0500
committerGravatar Jorge Aparicio <japaricious@gmail.com> 2017-03-11 23:15:39 -0500
commit173b5bc9750909408cfcd6140ddbf8a119dc7a18 (patch)
tree1ec4ef00b3634e23e4b7d62b7fc38f2cd8820d23 /src/exception.rs
parent0856d2c1d5d14d17014949a1d5c0a7c25e1e5bb0 (diff)
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add unsafe block
Diffstat (limited to 'src/exception.rs')
-rw-r--r--src/exception.rs19
1 files changed, 11 insertions, 8 deletions
diff --git a/src/exception.rs b/src/exception.rs
index 82401df..f5c8c28 100644
--- a/src/exception.rs
+++ b/src/exception.rs
@@ -153,7 +153,8 @@ pub const DEFAULT_HANDLERS: Handlers = Handlers {
// pointer (MSP), that way it points to the stacked registers
#[naked]
pub extern "C" fn default_handler<T>(_token: T)
- where T: Context
+where
+ T: Context,
{
// This is the actual exception handler. `_sf` is a pointer to the previous
// stack frame
@@ -167,16 +168,18 @@ pub extern "C" fn default_handler<T>(_token: T)
match () {
#[cfg(target_arch = "arm")]
() => {
- // "trampoline" to get to the real exception handler.
- asm!("mrs r0, MSP
+ unsafe {
+ // "trampoline" to get to the real exception handler.
+ asm!("mrs r0, MSP
ldr r1, [r0, #20]
b $0"
- :
- : "i"(handler as extern "C" fn(&StackedRegisters) -> !)
- :
- : "volatile");
+ :
+ : "i"(handler as extern "C" fn(&StackedRegisters) -> !)
+ :
+ : "volatile");
- ::core::intrinsics::unreachable()
+ ::core::intrinsics::unreachable()
+ }
}
#[cfg(not(target_arch = "arm"))]
() => {}