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| author |  Cliff L. Biffle <cliff@oxide.computer>
| 2020-07-04 10:27:51 -0700 |
|---|---|---|
| committer | Cliff L. Biffle <cliff@oxide.computer>
| 2020-07-05 08:41:25 -0700 |
| commit | a763f2bcef19c156ef56bb810f9b7401b4c99387 (patch) | |
| tree | 66c82004d10112306a8700aeb2216babffdbde5b /src/lib.rs | |
| parent | b70c25a9b887fc19ce94a9789a34c1a036186c76 (diff) | |
| download | cortex-m-a763f2bcef19c156ef56bb810f9b7401b4c99387.tar.gz cortex-m-a763f2bcef19c156ef56bb810f9b7401b4c99387.tar.zst cortex-m-a763f2bcef19c156ef56bb810f9b7401b4c99387.zip | |
Use assembly sequences to enable caches.
See #232, which this partially fixes -- there's still the question of
taking an interrupt in the midst of these sequences.
Diffstat (limited to 'src/lib.rs')
0 files changed, 0 insertions, 0 deletions