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authorGravatar bors[bot] <26634292+bors[bot]@users.noreply.github.com> 2023-01-04 01:26:29 +0000
committerGravatar GitHub <noreply@github.com> 2023-01-04 01:26:29 +0000
commitbb4a78208323260a161e68b2498438867f971bc5 (patch)
tree4389f08ef2ce88680673bc8fc737253d673a6c75 /src/lib.rs
parent641e41904313b13538ffeed10b930b1adabb025b (diff)
parent47398ccfae7b3b032995a29c0e2b05561f19aa28 (diff)
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Merge #458v0.7.7
458: cortex-m v0.7.7: add documentation for critical-section-single-core r=thejpster a=adamgreig This got missed in #448; this PR copies the documentation added in #451 to the v0.7.x branch. Co-authored-by: Adam Greig <adam@adamgreig.com>
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//! The disadvantage is that `inline-asm` requires a Rust version at least 1.59 to use the `asm!()`
//! macro. In the future 0.8 and above versions of `cortex-m`, this feature will always be enabled.
//!
+//! ## `critical-section-single-core`
+//!
+//! This feature enables a [`critical-section`](https://github.com/rust-embedded/critical-section)
+//! implementation suitable for single-core targets, based on disabling interrupts globally.
+//!
+//! It is **unsound** to enable it on multi-core targets or for code running in unprivileged mode,
+//! and may cause functional problems in systems where some interrupts must be not be disabled
+//! or critical sections are managed as part of an RTOS. In these cases, you should use
+//! a target-specific implementation instead, typically provided by a HAL or RTOS crate.
+//!
//! ## `cm7-r0p1`
//!
//! This feature enables workarounds for errata found on Cortex-M7 chips with revision r0p1. Some