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author | 2019-10-09 10:32:01 +0200 | |
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committer | 2019-10-29 07:45:53 +0100 | |
commit | 1608a660034bcc4334a6e0ca2d363c6b6bb94228 (patch) | |
tree | 593270b2e32c5595a77918b8638834d476dc27e9 /src/peripheral/cpuid.rs | |
parent | f505673246117276ecfab692e4b1303dc7496d32 (diff) | |
download | cortex-m-1608a660034bcc4334a6e0ca2d363c6b6bb94228.tar.gz cortex-m-1608a660034bcc4334a6e0ca2d363c6b6bb94228.tar.zst cortex-m-1608a660034bcc4334a6e0ca2d363c6b6bb94228.zip |
Add `#[inline]` to lots of trivial functions.
Diffstat (limited to 'src/peripheral/cpuid.rs')
-rw-r--r-- | src/peripheral/cpuid.rs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs index 1eb0869..119cce2 100644 --- a/src/peripheral/cpuid.rs +++ b/src/peripheral/cpuid.rs @@ -82,6 +82,7 @@ impl CPUID { /// * `ind`: select instruction cache or data/unified cache /// /// `level` is masked to be between 0 and 7. + #[inline] pub fn select_cache(&mut self, level: u8, ind: CsselrCacheType) { const CSSELR_IND_POS: u32 = 0; const CSSELR_IND_MASK: u32 = 1 << CSSELR_IND_POS; @@ -97,6 +98,7 @@ impl CPUID { } /// Returns the number of sets and ways in the selected cache + #[inline] pub fn cache_num_sets_ways(&mut self, level: u8, ind: CsselrCacheType) -> (u16, u16) { const CCSIDR_NUMSETS_POS: u32 = 13; const CCSIDR_NUMSETS_MASK: u32 = 0x7FFF << CCSIDR_NUMSETS_POS; |