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| author |  Adam Greig <adam@adamgreig.com>
| 2019-07-29 13:52:29 -0600 |
|---|---|---|
| committer | Adam Greig <adam@adamgreig.com>
| 2019-07-29 13:52:29 -0600 |
| commit | ac7eaef31a01258a90aa786bbce4d47b17e207c6 (patch) | |
| tree | 2849d31f22193c432ee255527633a1c5fa072fca /src/peripheral/cpuid.rs | |
| parent | 6a213910f7f8920906c2f8882cbc1f1a3ebc3627 (diff) | |
| download | cortex-m-ac7eaef31a01258a90aa786bbce4d47b17e207c6.tar.gz cortex-m-ac7eaef31a01258a90aa786bbce4d47b17e207c6.tar.zst cortex-m-ac7eaef31a01258a90aa786bbce4d47b17e207c6.zip | |
Update for 2018 edition
Diffstat (limited to 'src/peripheral/cpuid.rs')
| -rw-r--r-- | src/peripheral/cpuid.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs index c79ad18..7b86ddc 100644 --- a/src/peripheral/cpuid.rs +++ b/src/peripheral/cpuid.rs @@ -5,7 +5,7 @@ use volatile_register::RO; use volatile_register::RW; #[cfg(not(armv6m))] -use peripheral::CPUID; +use crate::peripheral::CPUID; /// Register block #[repr(C)] @@ -104,7 +104,7 @@ impl CPUID { const CCSIDR_ASSOCIATIVITY_MASK: u32 = 0x3FF << CCSIDR_ASSOCIATIVITY_POS; self.select_cache(level, ind); - ::asm::dsb(); + crate::asm::dsb(); let ccsidr = self.ccsidr.read(); ( (1 + ((ccsidr & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_POS)) as u16, |