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| author |  Jorge Aparicio <japaricious@gmail.com>
| 2017-03-07 22:56:06 -0500 |
|---|---|---|
| committer | Jorge Aparicio <japaricious@gmail.com>
| 2017-03-07 22:58:33 -0500 |
| commit | c3a35c1b6cea81aa71e8832bca79ccafa492be02 (patch) | |
| tree | e868906d20c906d238be96cd5c07b07342f7a111 /src/peripheral/cpuid.rs | |
| parent | 9d3f3f323f3b7543d0b49e773aea2c68e535ec83 (diff) | |
| download | cortex-m-c3a35c1b6cea81aa71e8832bca79ccafa492be02.tar.gz cortex-m-c3a35c1b6cea81aa71e8832bca79ccafa492be02.tar.zst cortex-m-c3a35c1b6cea81aa71e8832bca79ccafa492be02.zip | |
revamp for memory safety
Diffstat (limited to 'src/peripheral/cpuid.rs')
| -rw-r--r-- | src/peripheral/cpuid.rs | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs deleted file mode 100644 index 0dc140f..0000000 --- a/src/peripheral/cpuid.rs +++ /dev/null @@ -1,30 +0,0 @@ -//! CPUID - -use volatile_register::RO; - -/// Registers -#[repr(C)] -pub struct Registers { - /// CPUID base - pub base: RO<u32>, - reserved0: [u32; 15], - /// Processor Feature - pub pfr: [RO<u32>; 2], - /// Debug Feature - pub dfr: RO<u32>, - /// Auxiliary Feature - pub afr: RO<u32>, - /// Memory Model Feature - pub mmfr: [RO<u32>; 4], - /// Instruction Set Attribute - pub isar: [RO<u32>; 5], - reserved1: u32, - /// Cache Level ID - pub clidr: RO<u32>, - /// Cache Type - pub ctr: RO<u32>, - /// Cache Size ID - pub ccsidr: RO<u32>, - /// Cache Size Selection - pub csselr: RO<u32>, -} |