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| author |  homunkulus <homunkulus@gmx.com>
| 2018-01-15 18:22:33 +0000 |
|---|---|---|
| committer | homunkulus <homunkulus@gmx.com>
| 2018-01-15 18:22:33 +0000 |
| commit | d52b84c6e7f942814b270db5606c7e5a94fbc99a (patch) | |
| tree | bf76dbf189aec84e4c532ed6ed751693b272124d /src/peripheral/cpuid.rs | |
| parent | bc31511494082273b90def2c3348f591ecb5b103 (diff) | |
| parent | a8962d44d46ef3c16b3e5fb645fead4731cd2b24 (diff) | |
| download | cortex-m-d52b84c6e7f942814b270db5606c7e5a94fbc99a.tar.gz cortex-m-d52b84c6e7f942814b270db5606c7e5a94fbc99a.tar.zst cortex-m-d52b84c6e7f942814b270db5606c7e5a94fbc99a.zip | |
Auto merge of #76 - japaric:thumbv6m, r=japaric
hide ARMv7-M only peripherals on thumbv6m-none-eabi
None
Diffstat (limited to 'src/peripheral/cpuid.rs')
| -rw-r--r-- | src/peripheral/cpuid.rs | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs index 624d5c5..94a2c20 100644 --- a/src/peripheral/cpuid.rs +++ b/src/peripheral/cpuid.rs @@ -1,10 +1,10 @@ //! CPUID use volatile_register::RO; -#[cfg(any(armv7m, test))] +#[cfg(any(armv7m, target_arch = "x86_64"))] use volatile_register::RW; -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] use peripheral::CPUID; /// Register block @@ -25,21 +25,21 @@ pub struct RegisterBlock { pub isar: [RO<u32>; 5], reserved1: u32, /// Cache Level ID - #[cfg(any(armv7m, test))] + #[cfg(any(armv7m, target_arch = "x86_64"))] pub clidr: RO<u32>, /// Cache Type - #[cfg(any(armv7m, test))] + #[cfg(any(armv7m, target_arch = "x86_64"))] pub ctr: RO<u32>, /// Cache Size ID - #[cfg(any(armv7m, test))] + #[cfg(any(armv7m, target_arch = "x86_64"))] pub ccsidr: RO<u32>, /// Cache Size Selection - #[cfg(any(armv7m, test))] + #[cfg(any(armv7m, target_arch = "x86_64"))] pub csselr: RW<u32>, } /// Type of cache to select on CSSELR writes. -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] pub enum CsselrCacheType { /// Select DCache or unified cache DataOrUnified = 0, @@ -47,7 +47,7 @@ pub enum CsselrCacheType { Instruction = 1, } -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] impl CPUID { /// Selects the current CCSIDR /// |