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author | 2016-09-27 18:35:29 -0500 | |
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committer | 2016-09-27 18:35:29 -0500 | |
commit | ddc7f255b57d0e6aeb9f3b1b7466b2e5c0c5fff0 (patch) | |
tree | ac8332c9d63b45082f81ce419045c9b16db1b270 /src/peripheral/cpuid.rs | |
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initial commit
Diffstat (limited to 'src/peripheral/cpuid.rs')
-rw-r--r-- | src/peripheral/cpuid.rs | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs new file mode 100644 index 0000000..0dc140f --- /dev/null +++ b/src/peripheral/cpuid.rs @@ -0,0 +1,30 @@ +//! CPUID + +use volatile_register::RO; + +/// Registers +#[repr(C)] +pub struct Registers { + /// CPUID base + pub base: RO<u32>, + reserved0: [u32; 15], + /// Processor Feature + pub pfr: [RO<u32>; 2], + /// Debug Feature + pub dfr: RO<u32>, + /// Auxiliary Feature + pub afr: RO<u32>, + /// Memory Model Feature + pub mmfr: [RO<u32>; 4], + /// Instruction Set Attribute + pub isar: [RO<u32>; 5], + reserved1: u32, + /// Cache Level ID + pub clidr: RO<u32>, + /// Cache Type + pub ctr: RO<u32>, + /// Cache Size ID + pub ccsidr: RO<u32>, + /// Cache Size Selection + pub csselr: RO<u32>, +} |