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| author |  Michael Watzko <michael@watzko.de>
| 2018-09-05 23:44:25 +0200 |
|---|---|---|
| committer | Michael Watzko <michael@watzko.de>
| 2018-09-05 23:44:25 +0200 |
| commit | 49a6daed832d0e25fd1d4fc828b3c804eb684c22 (patch) | |
| tree | 1a4479e9f301a9048aa0002ddf6b6cabf53b2aee /src/peripheral/dcb.rs | |
| parent | b739654348afde81475493a2431a9f3779f2c7fa (diff) | |
| download | cortex-m-49a6daed832d0e25fd1d4fc828b3c804eb684c22.tar.gz cortex-m-49a6daed832d0e25fd1d4fc828b3c804eb684c22.tar.zst cortex-m-49a6daed832d0e25fd1d4fc828b3c804eb684c22.zip | |
Move shift-constant 24 to BIT_TRACENA
Diffstat (limited to 'src/peripheral/dcb.rs')
| -rw-r--r-- | src/peripheral/dcb.rs | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index 5e6014a..fe73002 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -4,6 +4,8 @@ use volatile_register::{RW, WO}; use peripheral::DCB; +const BIT_TRACENA: u8 = 24; + /// Register block #[repr(C)] pub struct RegisterBlock { @@ -24,12 +26,12 @@ impl DCB { /// soft-reset, only on power reset. pub fn enable_trace(&mut self) { // set bit 24 / TRACENA - unsafe { self.demcr.modify(|w| w | (0x01 << 24)); } + unsafe { self.demcr.modify(|w| w | (0x01 << BIT_TRACENA)); } } /// Disables TRACE. See `DCB::enable_trace()` for more details pub fn disable_trace(&mut self) { // unset bit 24 / TRACENA - unsafe { self.demcr.modify(|w| w & !(0x01 << 24)); } + unsafe { self.demcr.modify(|w| w & !(0x01 << BIT_TRACENA)); } } } |