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author | 2017-11-21 15:56:16 +0100 | |
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committer | 2017-11-21 15:56:16 +0100 | |
commit | c6ed9ef43f6606f654c2392413ca8ed380a35056 (patch) | |
tree | d0291cc25ae95b99089fca9fb49c5b5826757413 /src/peripheral/dcb.rs | |
parent | 7e05e189c5195303f8693d442b71754f956fc81f (diff) | |
download | cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.tar.gz cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.tar.zst cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.zip |
turn peripherals into scoped singletons
Diffstat (limited to 'src/peripheral/dcb.rs')
-rw-r--r-- | src/peripheral/dcb.rs | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs new file mode 100644 index 0000000..02ec901 --- /dev/null +++ b/src/peripheral/dcb.rs @@ -0,0 +1,16 @@ +//! Debug Control Block + +use volatile_register::{RW, WO}; + +/// Register block +#[repr(C)] +pub struct RegisterBlock { + /// Debug Halting Control and Status + pub dhcsr: RW<u32>, + /// Debug Core Register Selector + pub dcrsr: WO<u32>, + /// Debug Core Register Data + pub dcrdr: RW<u32>, + /// Debug Exception and Monitor Control + pub demcr: RW<u32>, +} |