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authorGravatar Jorge Aparicio <jorge@japaric.io> 2017-12-22 11:20:22 +0100
committerGravatar Jorge Aparicio <jorge@japaric.io> 2017-12-23 19:08:04 +0100
commit80328e98f361bd7ea07e3376691130790dae71a3 (patch)
tree24cb226132889f8b535a31d9a3babc766776afa8 /src/peripheral/dwt.rs
parentbdc7ca96c5593e410c8f49025d2b0fced7607a4d (diff)
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revise peripheral API
closes #67
Diffstat (limited to 'src/peripheral/dwt.rs')
-rw-r--r--src/peripheral/dwt.rs22
1 files changed, 15 insertions, 7 deletions
diff --git a/src/peripheral/dwt.rs b/src/peripheral/dwt.rs
index b716369..84f002e 100644
--- a/src/peripheral/dwt.rs
+++ b/src/peripheral/dwt.rs
@@ -2,6 +2,8 @@
use volatile_register::{RO, RW, WO};
+use peripheral::DWT;
+
/// Register block
#[repr(C)]
pub struct RegisterBlock {
@@ -30,13 +32,6 @@ pub struct RegisterBlock {
pub lsr: RO<u32>,
}
-impl RegisterBlock {
- /// Enables the cycle counter
- pub fn enable_cycle_counter(&self) {
- unsafe { self.ctrl.modify(|r| r | 1) }
- }
-}
-
/// Comparator
#[repr(C)]
pub struct Comparator {
@@ -48,3 +43,16 @@ pub struct Comparator {
pub function: RW<u32>,
reserved: u32,
}
+
+impl DWT {
+ /// Enables the cycle counter
+ pub fn enable_cycle_counter(&mut self) {
+ unsafe { self.ctrl.modify(|r| r | 1) }
+ }
+
+ /// Returns the current clock cycle count
+ pub fn get_cycle_count() -> u32 {
+ // NOTE(unsafe) atomic read with no side effects
+ unsafe { (*Self::ptr()).cyccnt.read() }
+ }
+}