diff options
author | 2017-11-21 15:56:16 +0100 | |
---|---|---|
committer | 2017-11-21 15:56:16 +0100 | |
commit | c6ed9ef43f6606f654c2392413ca8ed380a35056 (patch) | |
tree | d0291cc25ae95b99089fca9fb49c5b5826757413 /src/peripheral/dwt.rs | |
parent | 7e05e189c5195303f8693d442b71754f956fc81f (diff) | |
download | cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.tar.gz cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.tar.zst cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.zip |
turn peripherals into scoped singletons
Diffstat (limited to 'src/peripheral/dwt.rs')
-rw-r--r-- | src/peripheral/dwt.rs | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/peripheral/dwt.rs b/src/peripheral/dwt.rs new file mode 100644 index 0000000..b716369 --- /dev/null +++ b/src/peripheral/dwt.rs @@ -0,0 +1,50 @@ +//! Data Watchpoint and Trace unit + +use volatile_register::{RO, RW, WO}; + +/// Register block +#[repr(C)] +pub struct RegisterBlock { + /// Control + pub ctrl: RW<u32>, + /// Cycle Count + pub cyccnt: RW<u32>, + /// CPI Count + pub cpicnt: RW<u32>, + /// Exception Overhead Count + pub exccnt: RW<u32>, + /// Sleep Count + pub sleepcnt: RW<u32>, + /// LSU Count + pub lsucnt: RW<u32>, + /// Folded-instruction Count + pub foldcnt: RW<u32>, + /// Program Counter Sample + pub pcsr: RO<u32>, + /// Comparators + pub c: [Comparator; 16], + reserved: [u32; 932], + /// Lock Access + pub lar: WO<u32>, + /// Lock Status + pub lsr: RO<u32>, +} + +impl RegisterBlock { + /// Enables the cycle counter + pub fn enable_cycle_counter(&self) { + unsafe { self.ctrl.modify(|r| r | 1) } + } +} + +/// Comparator +#[repr(C)] +pub struct Comparator { + /// Comparator + pub comp: RW<u32>, + /// Comparator Mask + pub mask: RW<u32>, + /// Comparator Function + pub function: RW<u32>, + reserved: u32, +} |