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author | 2017-03-07 22:56:06 -0500 | |
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committer | 2017-03-07 22:58:33 -0500 | |
commit | c3a35c1b6cea81aa71e8832bca79ccafa492be02 (patch) | |
tree | e868906d20c906d238be96cd5c07b07342f7a111 /src/peripheral/fpu.rs | |
parent | 9d3f3f323f3b7543d0b49e773aea2c68e535ec83 (diff) | |
download | cortex-m-c3a35c1b6cea81aa71e8832bca79ccafa492be02.tar.gz cortex-m-c3a35c1b6cea81aa71e8832bca79ccafa492be02.tar.zst cortex-m-c3a35c1b6cea81aa71e8832bca79ccafa492be02.zip |
revamp for memory safety
Diffstat (limited to 'src/peripheral/fpu.rs')
-rw-r--r-- | src/peripheral/fpu.rs | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/peripheral/fpu.rs b/src/peripheral/fpu.rs deleted file mode 100644 index 5bbf352..0000000 --- a/src/peripheral/fpu.rs +++ /dev/null @@ -1,17 +0,0 @@ -//! Floating Point Unit - -use volatile_register::{RO, RW}; - -/// Registers -#[repr(C)] -pub struct Registers { - reserved: u32, - /// Floating Point Context Control - pub fpccr: RW<u32>, - /// Floating Point Context Address - pub fpcar: RW<u32>, - /// Floating Point Default Status Control - pub fpdscr: RW<u32>, - /// Media and FP Feature - pub mvfr: [RO<u32>; 3], -} |