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author | 2017-11-21 15:56:16 +0100 | |
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committer | 2017-11-21 15:56:16 +0100 | |
commit | c6ed9ef43f6606f654c2392413ca8ed380a35056 (patch) | |
tree | d0291cc25ae95b99089fca9fb49c5b5826757413 /src/peripheral/fpu.rs | |
parent | 7e05e189c5195303f8693d442b71754f956fc81f (diff) | |
download | cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.tar.gz cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.tar.zst cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.zip |
turn peripherals into scoped singletons
Diffstat (limited to 'src/peripheral/fpu.rs')
-rw-r--r-- | src/peripheral/fpu.rs | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/peripheral/fpu.rs b/src/peripheral/fpu.rs new file mode 100644 index 0000000..ada8b7a --- /dev/null +++ b/src/peripheral/fpu.rs @@ -0,0 +1,22 @@ +//! Floating Point Unit + +#[cfg(any(has_fpu, test))] +use volatile_register::{RO, RW}; + +/// Register block +#[repr(C)] +pub struct RegisterBlock { + reserved: u32, + /// Floating Point Context Control + #[cfg(any(has_fpu, test))] + pub fpccr: RW<u32>, + /// Floating Point Context Address + #[cfg(any(has_fpu, test))] + pub fpcar: RW<u32>, + /// Floating Point Default Status Control + #[cfg(any(has_fpu, test))] + pub fpdscr: RW<u32>, + /// Media and FP Feature + #[cfg(any(has_fpu, test))] + pub mvfr: [RO<u32>; 3], +} |