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authorGravatar bors[bot] <26634292+bors[bot]@users.noreply.github.com> 2022-01-02 18:13:28 +0000
committerGravatar GitHub <noreply@github.com> 2022-01-02 18:13:28 +0000
commit2e2cb78a842f702f78f74e470216eb5139b4a264 (patch)
tree7ffcad44fe62db0117632bf41a32304170920097 /src/peripheral/mod.rs
parent4b536898ca8da6d20bd54d91fd7938aae0c538bf (diff)
parente62dee61f41df76922ee13a830a24bbec2f932f5 (diff)
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Merge #375v0.7.4
375: Prepare v0.7.4 r=thejpster a=adamgreig I've created a new branch, `v0.7.x`, which is currently at the latest non-breaking commit (so includes #346 #349 #347 #351 #339 #352 #348 #363 #362 #361 but does not include #342), to track the 0.7 series since master now contains breaking changes for v0.8. This PR (which targets the new branch) cherry-picks #372 #369 #374 and bumps the version to v0.7.4 (and updates CHANGELOG) ready for a new v0.7.4 release. Once complete I'll also backport the changelog entries and bump the version in master to 0.7.4. I think this is everything that should be in 0.7 -- the only excluded PRs from master are #342 and #367 I believe, and I don't think we have any open PRs targeting 0.7 either. Any other thoughts on items for inclusion in 0.7.4 (or other changelog entries I missed)? Co-authored-by: bors[bot] <26634292+bors[bot]@users.noreply.github.com> Co-authored-by: Adam Greig <adam@adamgreig.com>
Diffstat (limited to 'src/peripheral/mod.rs')
-rw-r--r--src/peripheral/mod.rs8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index 5c5e7ce..3756553 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -71,8 +71,8 @@ pub mod dcb;
pub mod dwt;
#[cfg(not(armv6m))]
pub mod fpb;
-// NOTE(target_arch) is for documentation purposes
-#[cfg(any(has_fpu, target_arch = "x86_64"))]
+// NOTE(native) is for documentation purposes
+#[cfg(any(has_fpu, native))]
pub mod fpu;
pub mod icb;
#[cfg(all(not(armv6m), not(armv8m_base)))]
@@ -405,7 +405,7 @@ pub struct FPU {
unsafe impl Send for FPU {}
-#[cfg(any(has_fpu, target_arch = "x86_64"))]
+#[cfg(any(has_fpu, native))]
impl FPU {
/// Pointer to the register block
pub const PTR: *const fpu::RegisterBlock = 0xE000_EF30 as *const _;
@@ -417,7 +417,7 @@ impl FPU {
}
}
-#[cfg(any(has_fpu, target_arch = "x86_64"))]
+#[cfg(any(has_fpu, native))]
impl ops::Deref for FPU {
type Target = self::fpu::RegisterBlock;