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authorGravatar bors[bot] <26634292+bors[bot]@users.noreply.github.com> 2021-09-23 22:42:08 +0000
committerGravatar GitHub <noreply@github.com> 2021-09-23 22:42:08 +0000
commit9e9ab9a8486fa649d448420bb25f7ef1ca53fcb9 (patch)
treeb96ca55f778297c1a4d4c203f423ff5476842bf0 /src/peripheral/mod.rs
parentbb49576aabf72f6b29f49090418c63f9ff241bc7 (diff)
parent7887d6d5415ab401d4ada96cc9ab44f35730da0b (diff)
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Merge #352
352: Add the Cortex-M7 TCM and cache access control registers. r=adamgreig a=rcls Add the Cortex-M7 TCM and cache access control registers. These are documented in the Cortex-M7 generic user guide (ARM DUI 0646C). I'm not sure what feature gate these should be on - should I add a new one for Cortex-M7? Currently I have them on `not(armv6m)` - they do not appear to be in the ARMv7M architecture documentation, so I presume they are M7 specific. Co-authored-by: Ralph Loader <ralph1loader@gmail.com>
Diffstat (limited to 'src/peripheral/mod.rs')
-rw-r--r--src/peripheral/mod.rs31
1 files changed, 31 insertions, 0 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index 8f5678d..463a6ec 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -60,6 +60,8 @@ use core::ops;
use crate::interrupt;
+#[cfg(cm7)]
+pub mod ac;
#[cfg(not(armv6m))]
pub mod cbp;
pub mod cpuid;
@@ -91,6 +93,10 @@ mod test;
#[allow(non_snake_case)]
#[allow(clippy::manual_non_exhaustive)]
pub struct Peripherals {
+ /// Cortex-M7 TCM and cache access control.
+ #[cfg(cm7)]
+ pub AC: AC,
+
/// Cache and branch predictor maintenance operations.
/// Not available on Armv6-M.
pub CBP: CBP,
@@ -172,6 +178,10 @@ impl Peripherals {
TAKEN = true;
Peripherals {
+ #[cfg(cm7)]
+ AC: AC {
+ _marker: PhantomData,
+ },
CBP: CBP {
_marker: PhantomData,
},
@@ -219,6 +229,27 @@ impl Peripherals {
}
}
+/// Access control
+#[cfg(cm7)]
+pub struct AC {
+ _marker: PhantomData<*const ()>,
+}
+
+#[cfg(cm7)]
+unsafe impl Send for AC {}
+
+#[cfg(cm7)]
+impl AC {
+ /// Pointer to the register block
+ pub const PTR: *const self::ac::RegisterBlock = 0xE000_EF90 as *const _;
+
+ /// Returns a pointer to the register block (to be deprecated in 0.7)
+ #[inline(always)]
+ pub const fn ptr() -> *const self::ac::RegisterBlock {
+ Self::PTR
+ }
+}
+
/// Cache and branch predictor maintenance operations
pub struct CBP {
_marker: PhantomData<*const ()>,