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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2020-07-18 18:56:49 +0000 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2020-07-18 18:56:49 +0000 |
| commit | 9021bcd85dd6364942dc20a7ad2e49c4600693b6 (patch) | |
| tree | 9b0a3b3c4cd35acfe9778b90e90563ada5231d2c /src/peripheral/mpu.rs | |
| parent | d91e843707932da5361fc5134e64e8e9a6c4301d (diff) | |
| parent | aff71801966b5c8348cc8a69379e5dbc2f8fc910 (diff) | |
| download | cortex-m-9021bcd85dd6364942dc20a7ad2e49c4600693b6.tar.gz cortex-m-9021bcd85dd6364942dc20a7ad2e49c4600693b6.tar.zst cortex-m-9021bcd85dd6364942dc20a7ad2e49c4600693b6.zip | |
Merge #247
247: Correct typo in RASR register aliases r=adamgreig a=orclev
Fixes the typo in the a1, a2, and a3 aliases of the RASR MPU register.
Co-authored-by: R. Kyle Murphy <orclev@gmail.com>
Diffstat (limited to 'src/peripheral/mpu.rs')
| -rw-r--r-- | src/peripheral/mpu.rs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/peripheral/mpu.rs b/src/peripheral/mpu.rs index 4d53eb5..b6fa869 100644 --- a/src/peripheral/mpu.rs +++ b/src/peripheral/mpu.rs @@ -18,16 +18,16 @@ pub struct RegisterBlock { pub rasr: RW<u32>, /// Alias 1 of RBAR pub rbar_a1: RW<u32>, - /// Alias 1 of RSAR - pub rsar_a1: RW<u32>, + /// Alias 1 of RASR + pub rasr_a1: RW<u32>, /// Alias 2 of RBAR pub rbar_a2: RW<u32>, - /// Alias 2 of RSAR - pub rsar_a2: RW<u32>, + /// Alias 2 of RASR + pub rasr_a2: RW<u32>, /// Alias 3 of RBAR pub rbar_a3: RW<u32>, - /// Alias 3 of RSAR - pub rsar_a3: RW<u32>, + /// Alias 3 of RASR + pub rasr_a3: RW<u32>, } /// Register block for ARMv8-M |