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author | 2017-11-21 15:56:16 +0100 | |
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committer | 2017-11-21 15:56:16 +0100 | |
commit | c6ed9ef43f6606f654c2392413ca8ed380a35056 (patch) | |
tree | d0291cc25ae95b99089fca9fb49c5b5826757413 /src/peripheral/mpu.rs | |
parent | 7e05e189c5195303f8693d442b71754f956fc81f (diff) | |
download | cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.tar.gz cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.tar.zst cortex-m-c6ed9ef43f6606f654c2392413ca8ed380a35056.zip |
turn peripherals into scoped singletons
Diffstat (limited to 'src/peripheral/mpu.rs')
-rw-r--r-- | src/peripheral/mpu.rs | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/peripheral/mpu.rs b/src/peripheral/mpu.rs new file mode 100644 index 0000000..09d06f0 --- /dev/null +++ b/src/peripheral/mpu.rs @@ -0,0 +1,30 @@ +//! Memory Protection Unit + +use volatile_register::{RO, RW}; + +/// Register block +#[repr(C)] +pub struct RegisterBlock { + /// Type + pub _type: RO<u32>, + /// Control + pub ctrl: RW<u32>, + /// Region Number + pub rnr: RW<u32>, + /// Region Base Address + pub rbar: RW<u32>, + /// Region Attribute and Size + pub rasr: RW<u32>, + /// Alias 1 of RBAR + pub rbar_a1: RW<u32>, + /// Alias 1 of RSAR + pub rsar_a1: RW<u32>, + /// Alias 2 of RBAR + pub rbar_a2: RW<u32>, + /// Alias 2 of RSAR + pub rsar_a2: RW<u32>, + /// Alias 3 of RBAR + pub rbar_a3: RW<u32>, + /// Alias 3 of RSAR + pub rsar_a3: RW<u32>, +} |