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authorGravatar bors[bot] <26634292+bors[bot]@users.noreply.github.com> 2020-01-15 23:30:46 +0000
committerGravatar GitHub <noreply@github.com> 2020-01-15 23:30:46 +0000
commit22d47dd75e9fb5004e0192666123d28f0a418310 (patch)
tree038b76435de6c21dce65dc7a241f376196efba9b /src/peripheral/nvic.rs
parent465c64dca26b3fbd8137720b1d24b13d56c5d5d8 (diff)
parentab8d4634fa34881a97f4c15bb0ecbde946c4107f (diff)
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Merge #191
191: Remove deprecated APIs and the `const-fn` feature r=adamgreig a=jonas-schievink Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
Diffstat (limited to 'src/peripheral/nvic.rs')
-rw-r--r--src/peripheral/nvic.rs49
1 files changed, 4 insertions, 45 deletions
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs
index 1ecfc6e..6627e60 100644
--- a/src/peripheral/nvic.rs
+++ b/src/peripheral/nvic.rs
@@ -38,7 +38,6 @@ pub struct RegisterBlock {
_reserved5: [u32; 48],
- #[cfg(not(armv6m))]
/// Interrupt Priority
///
/// On ARMv7-M, 124 word-sized registers are available. Each of those
@@ -50,9 +49,9 @@ pub struct RegisterBlock {
/// On ARMv6-M, the registers must only be accessed along word boundaries,
/// so convenient byte-sized representation wouldn't work on that
/// architecture.
+ #[cfg(not(armv6m))]
pub ipr: [RW<u8>; 496],
- #[cfg(armv6m)]
/// Interrupt Priority
///
/// On ARMv7-M, 124 word-sized registers are available. Each of those
@@ -64,18 +63,18 @@ pub struct RegisterBlock {
/// On ARMv6-M, the registers must only be accessed along word boundaries,
/// so convenient byte-sized representation wouldn't work on that
/// architecture.
+ #[cfg(armv6m)]
pub ipr: [RW<u32>; 8],
#[cfg(not(armv6m))]
_reserved6: [u32; 580],
- #[cfg(not(armv6m))]
/// Software Trigger Interrupt
+ #[cfg(not(armv6m))]
pub stir: WO<u32>,
}
impl NVIC {
- #[cfg(not(armv6m))]
/// Request an IRQ in software
///
/// Writing a value to the INTID field is the same as manually pending an interrupt by setting
@@ -83,6 +82,7 @@ impl NVIC {
/// `set_pending`.
///
/// This method is not available on ARMv6-M chips.
+ #[cfg(not(armv6m))]
#[inline]
pub fn request<I>(&mut self, interrupt: I)
where
@@ -95,16 +95,6 @@ impl NVIC {
}
}
- /// Clears `interrupt`'s pending state
- #[deprecated(since = "0.5.8", note = "Use `NVIC::unpend`")]
- #[inline]
- pub fn clear_pending<I>(&mut self, interrupt: I)
- where
- I: Nr,
- {
- Self::unpend(interrupt)
- }
-
/// Disables `interrupt`
#[inline]
pub fn mask<I>(interrupt: I)
@@ -129,27 +119,6 @@ impl NVIC {
(*Self::ptr()).iser[usize::from(nr / 32)].write(1 << (nr % 32))
}
- /// Disables `interrupt`
- #[deprecated(since = "0.6.1", note = "Use `NVIC::mask`")]
- #[inline]
- pub fn disable<I>(&mut self, interrupt: I)
- where
- I: Nr,
- {
- Self::mask(interrupt)
- }
-
- /// **WARNING** This method is a soundness hole in the API; it should actually be an `unsafe`
- /// function. Use `NVIC::unmask` which has the right unsafety.
- #[deprecated(since = "0.6.1", note = "Use `NVIC::unmask`")]
- #[inline]
- pub fn enable<I>(&mut self, interrupt: I)
- where
- I: Nr,
- {
- unsafe { Self::unmask(interrupt) }
- }
-
/// Returns the NVIC priority of `interrupt`
///
/// *NOTE* NVIC encodes priority in the highest bits of a byte so values like `1` and `2` map
@@ -228,16 +197,6 @@ impl NVIC {
unsafe { (*Self::ptr()).ispr[usize::from(nr / 32)].write(1 << (nr % 32)) }
}
- /// Forces `interrupt` into pending state
- #[deprecated(since = "0.5.8", note = "Use `NVIC::pend`")]
- #[inline]
- pub fn set_pending<I>(&mut self, interrupt: I)
- where
- I: Nr,
- {
- Self::pend(interrupt)
- }
-
/// Sets the "priority" of `interrupt` to `prio`
///
/// *NOTE* See [`get_priority`](struct.NVIC.html#method.get_priority) method for an explanation