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| author |  Rajiv Ranganath <rajiv.ranganath@gmail.com>
| 2018-07-13 19:52:38 +0530 |
|---|---|---|
| committer | Rajiv Ranganath <rajiv.ranganath@gmail.com>
| 2018-07-13 19:52:38 +0530 |
| commit | 733e6d6f1bbd99346d74f8d23310065335f4f04c (patch) | |
| tree | 6b1422ca8569c77e01f83a49ba69c08d43869999 /src/peripheral/scb.rs | |
| parent | 39172497729e827a6bb48f899a1facf5ceb2558b (diff) | |
| download | cortex-m-733e6d6f1bbd99346d74f8d23310065335f4f04c.tar.gz cortex-m-733e6d6f1bbd99346d74f8d23310065335f4f04c.tar.zst cortex-m-733e6d6f1bbd99346d74f8d23310065335f4f04c.zip | |
Rename `shcrs` to `shcsr` in `scb::RegisterBlock`
Commit `c290aa4e` introduced `shcrs` field to `scb::RegisterBlock`.
In CMSIS, this field is `shcsr`.
https://github.com/ARM-software/CMSIS_5/blob/5.3.0/CMSIS/Core/Include/core_cm4.h#L449
This patch changes `shcrs` to `shcsr`.
Signed-off-by: Rajiv Ranganath <rajiv.ranganath@gmail.com>
Diffstat (limited to 'src/peripheral/scb.rs')
| -rw-r--r-- | src/peripheral/scb.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 2ad0770..ba36093 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -51,7 +51,7 @@ pub struct RegisterBlock { pub shpr: [RW<u32>; 2], /// System Handler Control and State - pub shcrs: RW<u32>, + pub shcsr: RW<u32>, /// Configurable Fault Status (not present on Cortex-M0 variants) #[cfg(not(armv6m))] |