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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2021-09-23 22:42:08 +0000 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2021-09-23 22:42:08 +0000 |
| commit | 9e9ab9a8486fa649d448420bb25f7ef1ca53fcb9 (patch) | |
| tree | b96ca55f778297c1a4d4c203f423ff5476842bf0 /src/peripheral/scb.rs | |
| parent | bb49576aabf72f6b29f49090418c63f9ff241bc7 (diff) | |
| parent | 7887d6d5415ab401d4ada96cc9ab44f35730da0b (diff) | |
| download | cortex-m-9e9ab9a8486fa649d448420bb25f7ef1ca53fcb9.tar.gz cortex-m-9e9ab9a8486fa649d448420bb25f7ef1ca53fcb9.tar.zst cortex-m-9e9ab9a8486fa649d448420bb25f7ef1ca53fcb9.zip | |
Merge #352
352: Add the Cortex-M7 TCM and cache access control registers. r=adamgreig a=rcls
Add the Cortex-M7 TCM and cache access control registers.
These are documented in the Cortex-M7 generic user guide (ARM DUI 0646C).
I'm not sure what feature gate these should be on - should I add a new one for Cortex-M7? Currently I have them on `not(armv6m)` - they do not appear to be in the ARMv7M architecture documentation, so I presume they are M7 specific.
Co-authored-by: Ralph Loader <ralph1loader@gmail.com>
Diffstat (limited to 'src/peripheral/scb.rs')
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