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authorGravatar homunkulus <homunkulus@gmx.com> 2018-01-15 18:22:33 +0000
committerGravatar homunkulus <homunkulus@gmx.com> 2018-01-15 18:22:33 +0000
commitd52b84c6e7f942814b270db5606c7e5a94fbc99a (patch)
treebf76dbf189aec84e4c532ed6ed751693b272124d /src/peripheral/scb.rs
parentbc31511494082273b90def2c3348f591ecb5b103 (diff)
parenta8962d44d46ef3c16b3e5fb645fead4731cd2b24 (diff)
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Auto merge of #76 - japaric:thumbv6m, r=japaric
hide ARMv7-M only peripherals on thumbv6m-none-eabi None
Diffstat (limited to 'src/peripheral/scb.rs')
-rw-r--r--src/peripheral/scb.rs12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index 9a922c7..41f3825 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -2,11 +2,11 @@
use volatile_register::RW;
-#[cfg(any(armv7m, has_fpu))]
+#[cfg(any(armv7m, has_fpu, target_arch = "x86_64"))]
use super::{CBP, SCB};
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
use super::CPUID;
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
use super::cpuid::CsselrCacheType;
/// Register block
@@ -108,16 +108,16 @@ impl SCB {
}
}
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
mod scb_consts {
pub const SCB_CCR_IC_MASK: u32 = (1 << 17);
pub const SCB_CCR_DC_MASK: u32 = (1 << 16);
}
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
use self::scb_consts::*;
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
impl SCB {
/// Enables I-Cache if currently disabled
#[inline]