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authorGravatar bors[bot] <bors[bot]@users.noreply.github.com> 2019-03-12 21:29:39 +0000
committerGravatar bors[bot] <bors[bot]@users.noreply.github.com> 2019-03-12 21:29:39 +0000
commit3b574e88fb15d704b9c2dacbf643f7ca0fa706ca (patch)
treeb82cdea518f1b2eabd6431075de48aa6926bef35 /src/peripheral/test.rs
parentac5f677f575847c428767ee553fbd0289794262d (diff)
parent712aa294833012ee2f4d2ad4a065c6fba26873ed (diff)
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Merge #127
127: Cortex M0(+) DWT fixes r=adamgreig a=korken89 The current DWT setup has a lot of registers that are not available in Cortex-M0(+), fixes are added here. Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
Diffstat (limited to 'src/peripheral/test.rs')
-rw-r--r--src/peripheral/test.rs8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/peripheral/test.rs b/src/peripheral/test.rs
index 1f75818..d0d713a 100644
--- a/src/peripheral/test.rs
+++ b/src/peripheral/test.rs
@@ -29,11 +29,17 @@ fn dwt() {
let dwt = unsafe { &*::peripheral::DWT::ptr() };
assert_eq!(address(&dwt.ctrl), 0xE000_1000);
+ #[cfg(not(armv6m))]
assert_eq!(address(&dwt.cyccnt), 0xE000_1004);
+ #[cfg(not(armv6m))]
assert_eq!(address(&dwt.cpicnt), 0xE000_1008);
+ #[cfg(not(armv6m))]
assert_eq!(address(&dwt.exccnt), 0xE000_100C);
+ #[cfg(not(armv6m))]
assert_eq!(address(&dwt.sleepcnt), 0xE000_1010);
+ #[cfg(not(armv6m))]
assert_eq!(address(&dwt.lsucnt), 0xE000_1014);
+ #[cfg(not(armv6m))]
assert_eq!(address(&dwt.foldcnt), 0xE000_1018);
assert_eq!(address(&dwt.pcsr), 0xE000_101C);
assert_eq!(address(&dwt.c[0].comp), 0xE000_1020);
@@ -42,7 +48,9 @@ fn dwt() {
assert_eq!(address(&dwt.c[1].comp), 0xE000_1030);
assert_eq!(address(&dwt.c[1].mask), 0xE000_1034);
assert_eq!(address(&dwt.c[1].function), 0xE000_1038);
+ #[cfg(not(armv6m))]
assert_eq!(address(&dwt.lar), 0xE000_1FB0);
+ #[cfg(not(armv6m))]
assert_eq!(address(&dwt.lsr), 0xE000_1FB4);
}