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author | 2017-12-09 10:03:39 +0000 | |
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committer | 2017-12-09 10:03:39 +0000 | |
commit | ce5bee6e37b4127040224523a1af85c275401a18 (patch) | |
tree | bc6033773fa2c8959d6de6d8b673902141f17c84 /src/peripheral/tpiu.rs | |
parent | 7e05e189c5195303f8693d442b71754f956fc81f (diff) | |
parent | 0b45ea4bd486565da5d78793dcb4718afb4f4387 (diff) | |
download | cortex-m-ce5bee6e37b4127040224523a1af85c275401a18.tar.gz cortex-m-ce5bee6e37b4127040224523a1af85c275401a18.tar.zst cortex-m-ce5bee6e37b4127040224523a1af85c275401a18.zip |
Auto merge of #65 - japaric:singletons, r=japaric
turn peripherals into scoped singletons
See this RFC for details: japaric/svd2rust#157
Diffstat (limited to 'src/peripheral/tpiu.rs')
-rw-r--r-- | src/peripheral/tpiu.rs | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/peripheral/tpiu.rs b/src/peripheral/tpiu.rs new file mode 100644 index 0000000..7a08805 --- /dev/null +++ b/src/peripheral/tpiu.rs @@ -0,0 +1,29 @@ +//! Trace Port Interface Unit; + +use volatile_register::{RO, RW, WO}; + +/// Register block +#[repr(C)] +pub struct RegisterBlock { + /// Supported Parallel Port Sizes + pub sspsr: RO<u32>, + /// Current Parallel Port Size + pub cspsr: RW<u32>, + reserved0: [u32; 2], + /// Asynchronous Clock Prescaler + pub acpr: RW<u32>, + reserved1: [u32; 55], + /// Selected Pin Control + pub sppr: RW<u32>, + reserved2: [u32; 132], + /// Formatter and Flush Control + pub ffcr: RW<u32>, + reserved3: [u32; 810], + /// Lock Access + pub lar: WO<u32>, + /// Lock Status + pub lsr: RO<u32>, + reserved4: [u32; 4], + /// TPIU Type + pub _type: RO<u32>, +} |