Add doc comments

1 files changed, 12 insertions, 0 deletions

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 22f6ce1..3ae6248 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -1,11 +1,13 @@
 //! Floating-point Status Control Register
 
+/// Floating-point Status Control Register
 #[allow(clippy::missing_inline_in_public_items)]
 #[derive(Clone, Copy, Debug)]
 pub struct Fpscr {
     bits: u32,
 }
 
+//! Rounding mode
 #[derive(Clone, Copy, Debug)]
 pub enum RMode {
     Nearest,
@@ -45,21 +47,25 @@ impl Fpscr {
         self.bits & (1 << 28) != 0
     }
 
+    //! Read the Alternative Half Precision bit
     #[inline]
     pub fn ahp(self) -> bool {
         if self.bits & (1 << 26) != 0
     }
 
+    //! Read the Default NaN mode bit
     #[inline]
     pub fn dn(self) -> bool {
         if self.bits & (1 << 25) != 0
     }
 
+    //! Read the Flush to Zero mode bit
     #[inline]
     pub fn fz(self) -> bool {
         if self.bits & (1 << 24) != 0
     }
 
+    //! Read the Rounding Mode control field
     #[inline]
     pub fn rmode(self) -> RMode {
         match self.bits & (3 << 22) {
@@ -70,31 +76,37 @@ impl Fpscr {
         }
     }
 
+    //! Read the Input Denormal cumulative exception bit
     #[inline]
     pub fn idc(self) -> bool {
         if self.bits & (1 << 7) != 0
     }
 
+    //! Read the Inexact cumulative exception bit
     #[inline]
     pub fn ixc(self) -> bool {
         if self.bits & (1 << 4) != 0
     }
 
+    //! Read the Underflow cumulative exception bit
     #[inline]
     pub fn ufc(self) -> bool {
         if self.bits & (1 << 3) != 0
     }
 
+    //! Read the Overflow cumulative exception bit
     #[inline]
     pub fn ofc(self) -> bool {
         if self.bits & (1 << 2) != 0
     }
 
+    //! Read the Division by Zero cumulative exception bit
     #[inline]
     pub fn dzc(self) -> bool {
         if self.bits & (1 << 1) != 0
     }
 
+    //! Read the Invalid Operation cumulative exception bit
     #[inline]
     pub fn ioc(self) -> bool {
         if self.bits & (1 << 0) != 0