Merge asm implementations

14 files changed, 63 insertions, 445 deletions

diff --git a/src/register/apsr.rs b/src/register/apsr.rs
index 3db8aeb..b81d892 100644
--- a/src/register/apsr.rs
+++ b/src/register/apsr.rs
@@ -50,17 +50,6 @@ impl Apsr {
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
 pub fn read() -> Apsr {
-    match () {
-        #[cfg(cortex_m)]
-        () => {
-            let r: u32;
-            unsafe {
-                llvm_asm!("mrs $0, APSR" : "=r"(r) ::: "volatile");
-            }
-            Apsr { bits: r }
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    let bits: u32 = call_asm!(__apsr_r() -> u32);
+    Apsr { bits }
 }
diff --git a/src/register/basepri.rs b/src/register/basepri.rs
index 6caf938..07084cd 100644
--- a/src/register/basepri.rs
+++ b/src/register/basepri.rs
@@ -3,28 +3,7 @@
 /// Reads the CPU register
 #[inline]
 pub fn read() -> u8 {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => {
-            let r: u32;
-            unsafe {
-                llvm_asm!("mrs $0, BASEPRI" : "=r"(r) ::: "volatile");
-            }
-            r as u8
-        }
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => unsafe {
-            extern "C" {
-                fn __basepri_r() -> u8;
-            }
-
-            __basepri_r()
-        },
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    call_asm!(__basepri_r() -> u8)
 }
 
 /// Writes to the CPU register
@@ -32,39 +11,14 @@ pub fn read() -> u8 {
 /// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
 /// `cm7-r0p1` Cargo feature or this function WILL misbehave.
 #[inline]
-pub unsafe fn write(_basepri: u8) {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => match () {
-            #[cfg(not(feature = "cm7-r0p1"))]
-            () => llvm_asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
-            #[cfg(feature = "cm7-r0p1")]
-            () => crate::interrupt::free(
-                |_| llvm_asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
-            ),
-        },
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => match () {
-            #[cfg(not(feature = "cm7-r0p1"))]
-            () => {
-                extern "C" {
-                    fn __basepri_w(_: u8);
-                }
-
-                __basepri_w(_basepri);
-            }
-            #[cfg(feature = "cm7-r0p1")]
-            () => {
-                extern "C" {
-                    fn __basepri_w_cm7_r0p1(_: u8);
-                }
-
-                __basepri_w_cm7_r0p1(_basepri);
-            }
-        },
+pub unsafe fn write(basepri: u8) {
+    #[cfg(feature = "cm7-r0p1")]
+    {
+        call_asm!(__basepri_w_cm7_r0p1(basepri: u8));
+    }
 
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
+    #[cfg(not(feature = "cm7-r0p1"))]
+    {
+        call_asm!(__basepri_w(basepri: u8));
     }
 }
diff --git a/src/register/basepri_max.rs b/src/register/basepri_max.rs
index 0e66f69..cea3838 100644
--- a/src/register/basepri_max.rs
+++ b/src/register/basepri_max.rs
@@ -8,43 +8,14 @@
 /// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
 /// `cm7-r0p1` Cargo feature or this function WILL misbehave.
 #[inline]
-pub fn write(_basepri: u8) {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => unsafe {
-            match () {
-                #[cfg(not(feature = "cm7-r0p1"))]
-                () => llvm_asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
-                #[cfg(feature = "cm7-r0p1")]
-                () => crate::interrupt::free(
-                    |_| llvm_asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
-                ),
-            }
-        },
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => unsafe {
-            match () {
-                #[cfg(not(feature = "cm7-r0p1"))]
-                () => {
-                    extern "C" {
-                        fn __basepri_max(_: u8);
-                    }
-
-                    __basepri_max(_basepri)
-                }
-                #[cfg(feature = "cm7-r0p1")]
-                () => {
-                    extern "C" {
-                        fn __basepri_max_cm7_r0p1(_: u8);
-                    }
-
-                    __basepri_max_cm7_r0p1(_basepri)
-                }
-            }
-        },
+pub fn write(basepri: u8) {
+    #[cfg(feature = "cm7-r0p1")]
+    {
+        call_asm!(__basepri_max_cm7_r0p1(basepri: u8));
+    }
 
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
+    #[cfg(not(feature = "cm7-r0p1"))]
+    {
+        call_asm!(__basepri_max(basepri: u8));
     }
 }
diff --git a/src/register/control.rs b/src/register/control.rs
index 211b532..938b10f 100644
--- a/src/register/control.rs
+++ b/src/register/control.rs
@@ -156,58 +156,13 @@ impl Fpca {
 /// Reads the CPU register
 #[inline]
 pub fn read() -> Control {
-    match () {
-        #[cfg(cortex_m)]
-        () => {
-            let r = match () {
-                #[cfg(feature = "inline-asm")]
-                () => {
-                    let r: u32;
-                    unsafe { llvm_asm!("mrs $0, CONTROL" : "=r"(r) ::: "volatile") }
-                    r
-                }
-
-                #[cfg(not(feature = "inline-asm"))]
-                () => unsafe {
-                    extern "C" {
-                        fn __control_r() -> u32;
-                    }
-
-                    __control_r()
-                },
-            };
-
-            Control { bits: r }
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    let bits: u32 = call_asm!(__control_r() -> u32);
+    Control { bits }
 }
 
 /// Writes to the CPU register.
 #[inline]
-pub unsafe fn write(_control: Control) {
-    match () {
-        #[cfg(cortex_m)]
-        () => match () {
-            #[cfg(feature = "inline-asm")]
-            () => {
-                let control = _control.bits();
-                llvm_asm!("msr CONTROL, $0" :: "r"(control) : "memory" : "volatile");
-            }
-
-            #[cfg(not(feature = "inline-asm"))]
-            () => {
-                extern "C" {
-                    fn __control_w(bits: u32);
-                }
-
-                __control_w(_control.bits());
-            }
-        },
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+pub unsafe fn write(control: Control) {
+    let control = control.bits();
+    call_asm!(__control_w(control: u32));
 }
diff --git a/src/register/faultmask.rs b/src/register/faultmask.rs
index 06f60fe..1f19d97 100644
--- a/src/register/faultmask.rs
+++ b/src/register/faultmask.rs
@@ -27,36 +27,10 @@ impl Faultmask {
 /// Reads the CPU register
 #[inline]
 pub fn read() -> Faultmask {
-    match () {
-        #[cfg(cortex_m)]
-        () => {
-            let r = match () {
-                #[cfg(feature = "inline-asm")]
-                () => {
-                    let r: u32;
-                    unsafe { llvm_asm!("mrs $0, FAULTMASK" : "=r"(r) ::: "volatile") }
-                    r
-                }
-
-                #[cfg(not(feature = "inline-asm"))]
-                () => unsafe {
-                    extern "C" {
-                        fn __faultmask() -> u32;
-
-                    }
-
-                    __faultmask()
-                },
-            };
-
-            if r & (1 << 0) == (1 << 0) {
-                Faultmask::Inactive
-            } else {
-                Faultmask::Active
-            }
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
+    let r: u32 = call_asm!(__faultmask_r() -> u32);
+    if r & (1 << 0) == (1 << 0) {
+        Faultmask::Inactive
+    } else {
+        Faultmask::Active
     }
 }
diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 2ca00e1..dd538e9 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -295,49 +295,13 @@ impl RMode {
 /// Read the FPSCR register
 #[inline]
 pub fn read() -> Fpscr {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => {
-            let r: u32;
-            unsafe {
-                llvm_asm!("vmrs $0, fpscr" : "=r"(r) ::: "volatile");
-            }
-            Fpscr::from_bits(r)
-        }
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => unsafe {
-            extern "C" {
-                fn __get_FPSCR() -> u32;
-            }
-            Fpscr::from_bits(__get_FPSCR())
-        },
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    let r: u32 = call_asm!(__fpscr_r() -> u32);
+    Fpscr::from_bits(r)
 }
 
 /// Set the value of the FPSCR register
 #[inline]
-pub unsafe fn write(_fspcr: Fpscr) {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => {
-            let bits = _fspcr.bits();
-            llvm_asm!("vmsr fpscr, $0" :: "r"(bits) :: "volatile");
-        }
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => {
-            extern "C" {
-                fn __set_FPSCR(bits: u32);
-            }
-
-            __set_FPSCR(_fspcr.bits());
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+pub unsafe fn write(fpscr: Fpscr) {
+    let fpscr = fpscr.bits();
+    call_asm!(__fpscr_w(fpscr: u32));
 }
diff --git a/src/register/lr.rs b/src/register/lr.rs
index 6919e10..1aa546c 100644
--- a/src/register/lr.rs
+++ b/src/register/lr.rs
@@ -5,29 +5,13 @@
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
 pub fn read() -> u32 {
-    match () {
-        #[cfg(cortex_m)]
-        () => {
-            let r: u32;
-            unsafe { llvm_asm!("mov $0,R14" : "=r"(r) ::: "volatile") }
-            r
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    call_asm!(__lr_r() -> u32)
 }
 
 /// Writes `bits` to the CPU register
 ///
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
-pub unsafe fn write(_bits: u32) {
-    match () {
-        #[cfg(cortex_m)]
-        () => llvm_asm!("mov R14,$0" :: "r"(_bits) :: "volatile"),
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+pub unsafe fn write(bits: u32) {
+    call_asm!(__lr_w(bits: u32));
 }
diff --git a/src/register/mod.rs b/src/register/mod.rs
index efbe6ef..48d157a 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -58,11 +58,11 @@ pub mod psplim;
 
 // Accessing these registers requires inline assembly because their contents are tied to the current
 // stack frame
-#[cfg(any(feature = "inline-asm", target_arch = "x86_64"))]
+#[cfg(feature = "inline-asm")]
 pub mod apsr;
 
-#[cfg(any(feature = "inline-asm", target_arch = "x86_64"))]
+#[cfg(feature = "inline-asm")]
 pub mod lr;
 
-#[cfg(any(feature = "inline-asm", target_arch = "x86_64"))]
+#[cfg(feature = "inline-asm")]
 pub mod pc;
diff --git a/src/register/msp.rs b/src/register/msp.rs
index b5460ed..275023d 100644
--- a/src/register/msp.rs
+++ b/src/register/msp.rs
@@ -3,45 +3,11 @@
 /// Reads the CPU register
 #[inline]
 pub fn read() -> u32 {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => {
-            let r;
-            unsafe { llvm_asm!("mrs $0,MSP" : "=r"(r) ::: "volatile") }
-            r
-        }
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => unsafe {
-            extern "C" {
-                fn __msp_r() -> u32;
-            }
-
-            __msp_r()
-        },
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    call_asm!(__msp_r() -> u32)
 }
 
 /// Writes `bits` to the CPU register
 #[inline]
-pub unsafe fn write(_bits: u32) {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => llvm_asm!("msr MSP,$0" :: "r"(_bits) :: "volatile"),
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => {
-            extern "C" {
-                fn __msp_w(_: u32);
-            }
-
-            __msp_w(_bits);
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+pub unsafe fn write(bits: u32) {
+    call_asm!(__msp_w(bits: u32));
 }
diff --git a/src/register/msplim.rs b/src/register/msplim.rs
index 68915c4..ac6f9ed 100644
--- a/src/register/msplim.rs
+++ b/src/register/msplim.rs
@@ -3,45 +3,11 @@
 /// Reads the CPU register
 #[inline]
 pub fn read() -> u32 {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => {
-            let r;
-            unsafe { llvm_asm!("mrs $0,MSPLIM" : "=r"(r) ::: "volatile") }
-            r
-        }
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => unsafe {
-            extern "C" {
-                fn __msplim_r() -> u32;
-            }
-
-            __msplim_r()
-        },
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    call_asm!(__msplim_r() -> u32)
 }
 
 /// Writes `bits` to the CPU register
 #[inline]
-pub unsafe fn write(_bits: u32) {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => llvm_asm!("msr MSPLIM,$0" :: "r"(_bits) :: "volatile"),
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => {
-            extern "C" {
-                fn __msplim_w(_: u32);
-            }
-
-            __msplim_w(_bits);
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+pub unsafe fn write(bits: u32) {
+    call_asm!(__msplim_w(bits: u32))
 }
diff --git a/src/register/pc.rs b/src/register/pc.rs
index f4486c4..0b33629 100644
--- a/src/register/pc.rs
+++ b/src/register/pc.rs
@@ -5,29 +5,13 @@
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
 pub fn read() -> u32 {
-    match () {
-        #[cfg(cortex_m)]
-        () => {
-            let r;
-            unsafe { llvm_asm!("mov $0,R15" : "=r"(r) ::: "volatile") }
-            r
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    call_asm!(__pc_r() -> u32)
 }
 
 /// Writes `bits` to the CPU register
 ///
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
-pub unsafe fn write(_bits: u32) {
-    match () {
-        #[cfg(cortex_m)]
-        () => llvm_asm!("mov R15,$0" :: "r"(_bits) :: "volatile"),
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+pub unsafe fn write(bits: u32) {
+    call_asm!(__pc_w(bits: u32));
 }
diff --git a/src/register/primask.rs b/src/register/primask.rs
index 4b6df3c..20692a2 100644
--- a/src/register/primask.rs
+++ b/src/register/primask.rs
@@ -27,35 +27,14 @@ impl Primask {
 /// Reads the CPU register
 #[inline]
 pub fn read() -> Primask {
-    match () {
-        #[cfg(cortex_m)]
-        () => {
-            let r = match () {
-                #[cfg(feature = "inline-asm")]
-                () => {
-                    let r: u32;
-                    unsafe { llvm_asm!("mrs $0, PRIMASK" : "=r"(r) ::: "volatile") }
-                    r
-                }
-
-                #[cfg(not(feature = "inline-asm"))]
-                () => {
-                    extern "C" {
-                        fn __primask() -> u32;
-                    }
-
-                    unsafe { __primask() }
-                }
-            };
-
-            if r & (1 << 0) == (1 << 0) {
-                Primask::Inactive
-            } else {
-                Primask::Active
-            }
-        }
+    fn read_raw() -> u32 {
+        call_asm!(__primask_r() -> u32)
+    }
 
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
+    let r = read_raw();
+    if r & (1 << 0) == (1 << 0) {
+        Primask::Inactive
+    } else {
+        Primask::Active
     }
 }
diff --git a/src/register/psp.rs b/src/register/psp.rs
index c020e4f..0bca22c 100644
--- a/src/register/psp.rs
+++ b/src/register/psp.rs
@@ -3,45 +3,11 @@
 /// Reads the CPU register
 #[inline]
 pub fn read() -> u32 {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => {
-            let r;
-            unsafe { llvm_asm!("mrs $0,PSP" : "=r"(r) ::: "volatile") }
-            r
-        }
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => unsafe {
-            extern "C" {
-                fn __psp_r() -> u32;
-            }
-
-            __psp_r()
-        },
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    call_asm!(__psp_r() -> u32)
 }
 
 /// Writes `bits` to the CPU register
 #[inline]
-pub unsafe fn write(_bits: u32) {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => llvm_asm!("msr PSP,$0" :: "r"(_bits) :: "volatile"),
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => {
-            extern "C" {
-                fn __psp_w(_: u32);
-            }
-
-            __psp_w(_bits);
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+pub unsafe fn write(bits: u32) {
+    call_asm!(__psp_w(bits: u32))
 }
diff --git a/src/register/psplim.rs b/src/register/psplim.rs
index 8cb8f1c..8ee1e94 100644
--- a/src/register/psplim.rs
+++ b/src/register/psplim.rs
@@ -3,45 +3,11 @@
 /// Reads the CPU register
 #[inline]
 pub fn read() -> u32 {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => {
-            let r;
-            unsafe { llvm_asm!("mrs $0,PSPLIM" : "=r"(r) ::: "volatile") }
-            r
-        }
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => unsafe {
-            extern "C" {
-                fn __psplim_r() -> u32;
-            }
-
-            __psplim_r()
-        },
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+    call_asm!(__psplim_r() -> u32)
 }
 
 /// Writes `bits` to the CPU register
 #[inline]
-pub unsafe fn write(_bits: u32) {
-    match () {
-        #[cfg(all(cortex_m, feature = "inline-asm"))]
-        () => llvm_asm!("msr PSPLIM,$0" :: "r"(_bits) :: "volatile"),
-
-        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => {
-            extern "C" {
-                fn __psplim_w(_: u32);
-            }
-
-            __psplim_w(_bits);
-        }
-
-        #[cfg(not(cortex_m))]
-        () => unimplemented!(),
-    }
+pub unsafe fn write(bits: u32) {
+    call_asm!(__psplim_w(bits: u32))
 }