make compilable on stable

11 files changed, 198 insertions, 63 deletions

diff --git a/src/register/apsr.rs b/src/register/apsr.rs
index 60dd364..280fd24 100644
--- a/src/register/apsr.rs
+++ b/src/register/apsr.rs
@@ -42,7 +42,7 @@ impl Apsr {
 #[inline]
 pub fn read() -> Apsr {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(cortex_m)]
         () => {
             let r: u32;
             unsafe {
@@ -50,7 +50,8 @@ pub fn read() -> Apsr {
             }
             Apsr { bits: r }
         }
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
diff --git a/src/register/basepri.rs b/src/register/basepri.rs
index c9be9d3..086d8cf 100644
--- a/src/register/basepri.rs
+++ b/src/register/basepri.rs
@@ -4,7 +4,7 @@
 #[inline]
 pub fn read() -> u8 {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
         () => {
             let r: u32;
             unsafe {
@@ -12,7 +12,17 @@ pub fn read() -> u8 {
             }
             r as u8
         }
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __basepri_r() -> u8;
+            }
+
+            __basepri_r()
+        },
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
@@ -21,20 +31,29 @@ pub fn read() -> u8 {
 ///
 /// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
 /// `cm7-r0p1` Cargo feature or this function WILL misbehave.
-#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
 #[inline]
-pub unsafe fn write(basepri: u8) {
+pub unsafe fn write(_basepri: u8) {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
         () => match () {
             #[cfg(not(feature = "cm7-r0p1"))]
-            () => asm!("msr BASEPRI, $0" :: "r"(basepri) : "memory" : "volatile"),
+            () => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
             #[cfg(feature = "cm7-r0p1")]
-            () => asm!("cpsid i
-                        msr BASEPRI, $0
-                        cpsie i" :: "r"(basepri) : "memory" : "volatile"),
+            () => interrupt::free(
+                |_| asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
+            ),
         },
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __basepri_w(_: u8);
+            }
+
+            __basepri_w(_basepri);
+        },
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
diff --git a/src/register/basepri_max.rs b/src/register/basepri_max.rs
index c386e86..edcd11d 100644
--- a/src/register/basepri_max.rs
+++ b/src/register/basepri_max.rs
@@ -7,22 +7,31 @@
 ///
 /// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
 /// `cm7-r0p1` Cargo feature or this function WILL misbehave.
-#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
 #[inline]
-pub fn write(basepri: u8) {
+pub fn write(_basepri: u8) {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
         () => unsafe {
             match () {
                 #[cfg(not(feature = "cm7-r0p1"))]
-                () => asm!("msr BASEPRI_MAX, $0" :: "r"(basepri) : "memory" : "volatile"),
+                () => asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
                 #[cfg(feature = "cm7-r0p1")]
-                () => asm!("cpsid i
-                            msr BASEPRI_MAX, $0
-                            cpsie i" :: "r"(basepri) : "memory" : "volatile"),
+                () => interrupt::free(
+                    |_| asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
+                ),
             }
         },
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __basepri_max(_: u8);
+            }
+
+            __basepri_max(_basepri)
+        },
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
diff --git a/src/register/control.rs b/src/register/control.rs
index 93c497f..b6b6676 100644
--- a/src/register/control.rs
+++ b/src/register/control.rs
@@ -107,13 +107,30 @@ impl Fpca {
 #[inline]
 pub fn read() -> Control {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(cortex_m)]
         () => {
-            let r: u32;
-            unsafe { asm!("mrs $0, CONTROL" : "=r"(r) ::: "volatile") }
+            let r = match () {
+                #[cfg(feature = "inline-asm")]
+                () => {
+                    let r: u32;
+                    unsafe { asm!("mrs $0, CONTROL" : "=r"(r) ::: "volatile") }
+                    r
+                }
+
+                #[cfg(not(feature = "inline-asm"))]
+                () => unsafe {
+                    extern "C" {
+                        fn __control() -> u32;
+                    }
+
+                    __control()
+                },
+            };
+
             Control { bits: r }
         }
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
diff --git a/src/register/faultmask.rs b/src/register/faultmask.rs
index 3e0980e..9cd1892 100644
--- a/src/register/faultmask.rs
+++ b/src/register/faultmask.rs
@@ -25,17 +25,35 @@ impl Faultmask {
 #[inline]
 pub fn read() -> Faultmask {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(cortex_m)]
         () => {
-            let r: u32;
-            unsafe { asm!("mrs $0, FAULTMASK" : "=r"(r) ::: "volatile") }
+            let r = match () {
+                #[cfg(feature = "inline-asm")]
+                () => {
+                    let r: u32;
+                    unsafe { asm!("mrs $0, FAULTMASK" : "=r"(r) ::: "volatile") }
+                    r
+                }
+
+                #[cfg(not(feature = "inline-asm"))]
+                () => unsafe {
+                    extern "C" {
+                        fn __faultmask() -> u32;
+
+                    }
+
+                    __faultmask()
+                },
+            };
+
             if r & (1 << 0) == (1 << 0) {
                 Faultmask::Inactive
             } else {
                 Faultmask::Active
             }
         }
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
diff --git a/src/register/lr.rs b/src/register/lr.rs
index ddbc07d..60828d0 100644
--- a/src/register/lr.rs
+++ b/src/register/lr.rs
@@ -4,25 +4,26 @@
 #[inline]
 pub fn read() -> u32 {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(cortex_m)]
         () => {
             let r: u32;
             unsafe { asm!("mov $0,R14" : "=r"(r) ::: "volatile") }
             r
         }
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
 
 /// Writes `bits` to the CPU register
-#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
 #[inline]
-pub unsafe fn write(bits: u32) {
+pub unsafe fn write(_bits: u32) {
     match () {
-        #[cfg(target_arch = "arm")]
-        () => asm!("mov R14,$0" :: "r"(bits) :: "volatile"),
-        #[cfg(not(target_arch = "arm"))]
+        #[cfg(cortex_m)]
+        () => asm!("mov R14,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
diff --git a/src/register/mod.rs b/src/register/mod.rs
index 17f6fda..37692c8 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -26,16 +26,30 @@
 //!
 //! - Cortex-M* Devices Generic User Guide - Section 2.1.3 Core registers
 
-pub mod apsr;
 #[cfg(not(armv6m))]
 pub mod basepri;
+
 #[cfg(not(armv6m))]
 pub mod basepri_max;
+
 pub mod control;
+
 #[cfg(not(armv6m))]
 pub mod faultmask;
-pub mod lr;
+
 pub mod msp;
-pub mod pc;
+
 pub mod primask;
+
 pub mod psp;
+
+// Accessing these registers requires inline assembly because their contents are tied to the current
+// stack frame
+#[cfg(feature = "nightly")]
+pub mod apsr;
+
+#[cfg(feature = "nightly")]
+pub mod lr;
+
+#[cfg(feature = "nightly")]
+pub mod pc;
diff --git a/src/register/msp.rs b/src/register/msp.rs
index 3b83353..082a7fc 100644
--- a/src/register/msp.rs
+++ b/src/register/msp.rs
@@ -4,25 +4,44 @@
 #[inline]
 pub fn read() -> u32 {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
         () => {
             let r;
             unsafe { asm!("mrs $0,MSP" : "=r"(r) ::: "volatile") }
             r
         }
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __msp_r() -> u32;
+            }
+
+            __msp_r()
+        },
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
 
 /// Writes `bits` to the CPU register
-#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
 #[inline]
-pub unsafe fn write(bits: u32) {
+pub unsafe fn write(_bits: u32) {
     match () {
-        #[cfg(target_arch = "arm")]
-        () => asm!("msr MSP,$0" :: "r"(bits) :: "volatile"),
-        #[cfg(not(target_arch = "arm"))]
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => asm!("msr MSP,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __msp_w(_: u32);
+            }
+
+            __msp_w(_bits);
+        }
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
diff --git a/src/register/pc.rs b/src/register/pc.rs
index 7a7ef19..b41383d 100644
--- a/src/register/pc.rs
+++ b/src/register/pc.rs
@@ -4,25 +4,26 @@
 #[inline]
 pub fn read() -> u32 {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(cortex_m)]
         () => {
             let r;
             unsafe { asm!("mov $0,R15" : "=r"(r) ::: "volatile") }
             r
         }
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
 
 /// Writes `bits` to the CPU register
-#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
 #[inline]
-pub unsafe fn write(bits: u32) {
+pub unsafe fn write(_bits: u32) {
     match () {
-        #[cfg(target_arch = "arm")]
-        () => asm!("mov R15,$0" :: "r"(bits) :: "volatile"),
-        #[cfg(not(target_arch = "arm"))]
+        #[cfg(cortex_m)]
+        () => asm!("mov R15,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
diff --git a/src/register/primask.rs b/src/register/primask.rs
index c9dc39a..cb8faf9 100644
--- a/src/register/primask.rs
+++ b/src/register/primask.rs
@@ -25,17 +25,34 @@ impl Primask {
 #[inline]
 pub fn read() -> Primask {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(cortex_m)]
         () => {
-            let r: u32;
-            unsafe { asm!("mrs $0, PRIMASK" : "=r"(r) ::: "volatile") }
+            let r = match () {
+                #[cfg(feature = "inline-asm")]
+                () => {
+                    let r: u32;
+                    unsafe { asm!("mrs $0, PRIMASK" : "=r"(r) ::: "volatile") }
+                    r
+                }
+
+                #[cfg(not(feature = "inline-asm"))]
+                () => {
+                    extern "C" {
+                        fn __primask() -> u32;
+                    }
+
+                    unsafe { __primask() }
+                }
+            };
+
             if r & (1 << 0) == (1 << 0) {
                 Primask::Inactive
             } else {
                 Primask::Active
             }
         }
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
diff --git a/src/register/psp.rs b/src/register/psp.rs
index d7232db..9f4889c 100644
--- a/src/register/psp.rs
+++ b/src/register/psp.rs
@@ -4,25 +4,44 @@
 #[inline]
 pub fn read() -> u32 {
     match () {
-        #[cfg(target_arch = "arm")]
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
         () => {
             let r;
             unsafe { asm!("mrs $0,PSP" : "=r"(r) ::: "volatile") }
             r
         }
-        #[cfg(not(target_arch = "arm"))]
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __psp_r() -> u32;
+            }
+
+            __psp_r()
+        }
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }
 
 /// Writes `bits` to the CPU register
-#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
 #[inline]
-pub unsafe fn write(bits: u32) {
+pub unsafe fn write(_bits: u32) {
     match () {
-        #[cfg(target_arch = "arm")]
-        () => asm!("msr PSP,$0" :: "r"(bits) :: "volatile"),
-        #[cfg(not(target_arch = "arm"))]
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => asm!("msr PSP,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __psp_w(_: u32);
+            }
+
+            __psp_w(_bits);
+        }
+
+        #[cfg(not(cortex_m))]
         () => unimplemented!(),
     }
 }