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author | 2023-02-26 23:12:38 +0000 | |
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committer | 2023-02-26 23:12:38 +0000 | |
commit | 067af8406f306bf8fba53ce738e441a8ba7fefe1 (patch) | |
tree | 40144c41f30e4c267837283e588db9b2ff65cfad /src | |
parent | 88c6f8637f4eccbb44f57be5bc10bcfc88fbb3c8 (diff) | |
parent | d6086d3f075be0060ffc3fd0559bcf662dc09a98 (diff) | |
download | cortex-m-067af8406f306bf8fba53ce738e441a8ba7fefe1.tar.gz cortex-m-067af8406f306bf8fba53ce738e441a8ba7fefe1.tar.zst cortex-m-067af8406f306bf8fba53ce738e441a8ba7fefe1.zip |
Merge #472
472: nvic: do not require `&mut self` for `request`. r=adamgreig a=Dirbaio
It's not needed, the register write is stateless/atomic.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Diffstat (limited to 'src')
-rw-r--r-- | src/peripheral/nvic.rs | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index 067c1d9..fccd6a2 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -94,15 +94,14 @@ impl NVIC { /// [`NVIC::pend`]: #method.pend #[cfg(not(armv6m))] #[inline] - pub fn request<I>(&mut self, interrupt: I) + pub fn request<I>(interrupt: I) where I: InterruptNumber, { let nr = interrupt.number(); - unsafe { - self.stir.write(u32::from(nr)); - } + // NOTE(ptr) this is a write to a stateless register + unsafe { (*Self::PTR).stir.write(u32::from(nr)) } } /// Disables `interrupt` |