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| author |  Brandon Matthews <bmatthews@zipcar.com>
| 2018-09-06 23:50:55 -0700 |
|---|---|---|
| committer |  Brandon Matthews <bmatthews@optimaltour.us>
| 2019-03-12 12:27:57 -0700 |
| commit | 2a15caa848f88420314786c3920d7c181335c686 (patch) | |
| tree | 0e8316105430019a195a8345c6995135100f3249 /src | |
| parent | 595fbd7346f6a1c393adec737b1587501c47bc4d (diff) | |
| download | cortex-m-2a15caa848f88420314786c3920d7c181335c686.tar.gz cortex-m-2a15caa848f88420314786c3920d7c181335c686.tar.zst cortex-m-2a15caa848f88420314786c3920d7c181335c686.zip | |
Fix rebase syntax error; disable STIR test on armv6m
Diffstat (limited to 'src')
| -rw-r--r-- | src/peripheral/dcb.rs | 1 | ||||
| -rw-r--r-- | src/peripheral/test.rs | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index 3d89c61..1d5680e 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -33,6 +33,7 @@ impl DCB { pub fn disable_trace(&mut self) { // unset bit 24 / TRCENA unsafe { self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA); } + } /// Is there a debugger attached? (see notes) /// diff --git a/src/peripheral/test.rs b/src/peripheral/test.rs index 1120dbb..49fd7cf 100644 --- a/src/peripheral/test.rs +++ b/src/peripheral/test.rs @@ -109,6 +109,7 @@ fn nvic() { assert_eq!(address(&nvic.icpr), 0xE000E280); assert_eq!(address(&nvic.iabr), 0xE000E300); assert_eq!(address(&nvic.ipr), 0xE000E400); + #[cfg(not(armv6m))] assert_eq!(address(&nvic.stir), 0xE000EF00); } |