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| author |  Michael Watzko <michael@watzko.de>
| 2018-09-05 23:53:48 +0200 |
|---|---|---|
| committer | Michael Watzko <michael@watzko.de>
| 2018-09-05 23:53:48 +0200 |
| commit | 385b3eb5b9f4f37503270fb3e9d7252a49d14c1b (patch) | |
| tree | f1841ae1925d23d639d642ea2a02f3761f1f9d8e /src | |
| parent | e6f511ade92b19c152d74d7ba6df2034dfd61bbe (diff) | |
| download | cortex-m-385b3eb5b9f4f37503270fb3e9d7252a49d14c1b.tar.gz cortex-m-385b3eb5b9f4f37503270fb3e9d7252a49d14c1b.tar.zst cortex-m-385b3eb5b9f4f37503270fb3e9d7252a49d14c1b.zip | |
Fix typo
Diffstat (limited to 'src')
| -rw-r--r-- | src/peripheral/dcb.rs | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index 94f7d96..363747c 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -4,7 +4,7 @@ use volatile_register::{RW, WO}; use peripheral::DCB; -const BIT_TRACENA: u32 = 0x01 << 24; +const BIT_TRCENA: u32 = 0x01 << 24; /// Register block #[repr(C)] @@ -25,13 +25,13 @@ impl DCB { /// As by STM documentation, this flag is not reset on /// soft-reset, only on power reset. pub fn enable_trace(&mut self) { - // set bit 24 / TRACENA - unsafe { self.demcr.modify(|w| w | BIT_TRACENA); } + // set bit 24 / TRCENA + unsafe { self.demcr.modify(|w| w | BIT_TRCENA); } } /// Disables TRACE. See `DCB::enable_trace()` for more details pub fn disable_trace(&mut self) { - // unset bit 24 / TRACENA - unsafe { self.demcr.modify(|w| w & !BIT_TRACENA); } + // unset bit 24 / TRCENA + unsafe { self.demcr.modify(|w| w & !BIT_TRCENA); } } } |