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author | 2017-06-12 11:57:25 +0100 | |
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committer | 2017-06-12 11:57:25 +0100 | |
commit | 414422f3a893c3a4795b22f7767858a90529c3f7 (patch) | |
tree | 9a53f8351e587fdf3f8ce67657e3692c2229f88e /src | |
parent | 07c40422eb0a6967847a9abbd34b00f99c2b119c (diff) | |
download | cortex-m-414422f3a893c3a4795b22f7767858a90529c3f7.tar.gz cortex-m-414422f3a893c3a4795b22f7767858a90529c3f7.tar.zst cortex-m-414422f3a893c3a4795b22f7767858a90529c3f7.zip |
Make invalidate_dcache private
Diffstat (limited to 'src')
-rw-r--r-- | src/peripheral/mod.rs | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index 5be5760..4884223 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -623,9 +623,13 @@ impl Scb { } /// Invalidates D-cache + /// + /// Note that calling this while the dcache is enabled will probably wipe out your + /// stack, depending on optimisations, breaking returning to the call point. + /// It's used immediately before enabling the dcache, but not exported publicly. #[cfg(armv7m)] #[inline] - pub fn invalidate_dcache(&self, cpuid: &Cpuid) { + fn invalidate_dcache(&self, cpuid: &Cpuid) { // All of CBP is write-only so no data races are possible let cbp = unsafe { &mut *CBP.get() }; |