aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGravatar Wim Looman <wim.looman@kiwi.ki> 2018-04-12 11:13:17 +0200
committerGravatar Wim Looman <wim.looman@kiwi.ki> 2018-04-12 11:13:17 +0200
commit5ec0518b0bc06e6f675b0709d50d8ca640660e5b (patch)
tree5aff7b61e07cbd88f2dfca9e5c0d32a86f8eab29 /src
parent3207cd89742d1ac79ac5c8219de8a6ff4b05c207 (diff)
downloadcortex-m-5ec0518b0bc06e6f675b0709d50d8ca640660e5b.tar.gz
cortex-m-5ec0518b0bc06e6f675b0709d50d8ca640660e5b.tar.zst
cortex-m-5ec0518b0bc06e6f675b0709d50d8ca640660e5b.zip
Add SEV assembly instruction
Diffstat (limited to 'src')
-rw-r--r--src/asm.rs11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/asm.rs b/src/asm.rs
index aab772e..9a2d481 100644
--- a/src/asm.rs
+++ b/src/asm.rs
@@ -47,6 +47,17 @@ pub fn wfi() {
}
}
+/// Send Event
+#[inline]
+pub fn sev() {
+ match () {
+ #[cfg(target_arch = "arm")]
+ () => unsafe { asm!("sev" :::: "volatile") },
+ #[cfg(not(target_arch = "arm"))]
+ () => unimplemented!(),
+ }
+}
+
/// Instruction Synchronization Barrier
///
/// Flushes the pipeline in the processor, so that all instructions following the `ISB` are fetched