simplify #[cfg]s

4 files changed, 54 insertions, 55 deletions

diff --git a/src/lib.rs b/src/lib.rs
index 9640363..df0ccbb 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -45,8 +45,7 @@ mod macros;
 
 pub mod asm;
 pub mod interrupt;
-// NOTE(target_arch = "x86_64") is used throughout this crate for documentation purposes
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub mod itm;
 pub mod peripheral;
 pub mod register;
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs
index e1d7637..d9dc027 100644
--- a/src/peripheral/cpuid.rs
+++ b/src/peripheral/cpuid.rs
@@ -65,7 +65,7 @@ pub struct RegisterBlock {
 }
 
 /// Type of cache to select on CSSELR writes.
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub enum CsselrCacheType {
     /// Select DCache or unified cache
     DataOrUnified = 0,
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index d46622d..ec50b71 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -84,23 +84,23 @@ use core::ops;
 
 use interrupt;
 
-// NOTE(target_arch) is for documentation purposes
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub mod cbp;
 pub mod cpuid;
 pub mod dcb;
 pub mod dwt;
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub mod fpb;
+// NOTE(target_arch) is for documentation purposes
 #[cfg(any(has_fpu, target_arch = "x86_64"))]
 pub mod fpu;
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub mod itm;
 pub mod mpu;
 pub mod nvic;
 pub mod scb;
 pub mod syst;
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub mod tpiu;
 
 #[cfg(test)]
@@ -112,7 +112,7 @@ mod test;
 #[allow(non_snake_case)]
 pub struct Peripherals {
     /// Cache and branch predictor maintenance operations
-    #[cfg(any(armv7m, target_arch = "x86_64"))]
+    #[cfg(not(armv6m))]
     pub CBP: CBP,
     /// CPUID
     pub CPUID: CPUID,
@@ -121,13 +121,13 @@ pub struct Peripherals {
     /// Data Watchpoint and Trace unit
     pub DWT: DWT,
     /// Flash Patch and Breakpoint unit
-    #[cfg(any(armv7m, target_arch = "x86_64"))]
+    #[cfg(not(armv6m))]
     pub FPB: FPB,
     /// Floating Point Unit
     #[cfg(any(has_fpu, target_arch = "x86_64"))]
     pub FPU: FPU,
     /// Instrumentation Trace Macrocell
-    #[cfg(any(armv7m, target_arch = "x86_64"))]
+    #[cfg(not(armv6m))]
     pub ITM: ITM,
     /// Memory Protection Unit
     pub MPU: MPU,
@@ -138,7 +138,7 @@ pub struct Peripherals {
     /// SysTick: System Timer
     pub SYST: SYST,
     /// Trace Port Interface Unit;
-    #[cfg(any(armv7m, target_arch = "x86_64"))]
+    #[cfg(not(armv6m))]
     pub TPIU: TPIU,
 }
 
@@ -167,7 +167,7 @@ impl Peripherals {
         CORE_PERIPHERALS = true;
 
         Peripherals {
-            #[cfg(any(armv7m, target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             CBP: CBP {
                 _marker: PhantomData,
             },
@@ -180,7 +180,7 @@ impl Peripherals {
             DWT: DWT {
                 _marker: PhantomData,
             },
-            #[cfg(any(armv7m, target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             FPB: FPB {
                 _marker: PhantomData,
             },
@@ -188,7 +188,7 @@ impl Peripherals {
             FPU: FPU {
                 _marker: PhantomData,
             },
-            #[cfg(any(armv7m, target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             ITM: ITM {
                 _marker: PhantomData,
             },
@@ -204,7 +204,7 @@ impl Peripherals {
             SYST: SYST {
                 _marker: PhantomData,
             },
-            #[cfg(any(armv7m, target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             TPIU: TPIU {
                 _marker: PhantomData,
             },
@@ -215,15 +215,15 @@ impl Peripherals {
 /// Cache and branch predictor maintenance operations
 ///
 /// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub struct CBP {
     _marker: PhantomData<*const ()>,
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 unsafe impl Send for CBP {}
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl CBP {
     pub(crate) unsafe fn new() -> Self {
         CBP {
@@ -237,7 +237,7 @@ impl CBP {
     }
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl ops::Deref for CBP {
     type Target = self::cbp::RegisterBlock;
 
@@ -315,15 +315,15 @@ impl ops::Deref for DWT {
 /// Flash Patch and Breakpoint unit
 ///
 /// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub struct FPB {
     _marker: PhantomData<*const ()>,
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 unsafe impl Send for FPB {}
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl FPB {
     /// Returns a pointer to the register block
     pub fn ptr() -> *const fpb::RegisterBlock {
@@ -331,7 +331,7 @@ impl FPB {
     }
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl ops::Deref for FPB {
     type Target = self::fpb::RegisterBlock;
 
@@ -371,15 +371,15 @@ impl ops::Deref for FPU {
 /// Instrumentation Trace Macrocell
 ///
 /// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub struct ITM {
     _marker: PhantomData<*const ()>,
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 unsafe impl Send for ITM {}
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl ITM {
     /// Returns a pointer to the register block
     pub fn ptr() -> *mut itm::RegisterBlock {
@@ -387,7 +387,7 @@ impl ITM {
     }
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl ops::Deref for ITM {
     type Target = self::itm::RegisterBlock;
 
@@ -396,7 +396,7 @@ impl ops::Deref for ITM {
     }
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl ops::DerefMut for ITM {
     fn deref_mut(&mut self) -> &mut Self::Target {
         unsafe { &mut *Self::ptr() }
@@ -494,15 +494,15 @@ impl ops::Deref for SYST {
 /// Trace Port Interface Unit;
 ///
 /// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 pub struct TPIU {
     _marker: PhantomData<*const ()>,
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 unsafe impl Send for TPIU {}
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl TPIU {
     /// Returns a pointer to the register block
     pub fn ptr() -> *const tpiu::RegisterBlock {
@@ -510,7 +510,7 @@ impl TPIU {
     }
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl ops::Deref for TPIU {
     type Target = self::tpiu::RegisterBlock;
 
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index 0a3a66a..58e083b 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -4,11 +4,11 @@ use core::ptr;
 
 use volatile_register::RW;
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 use super::cpuid::CsselrCacheType;
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 use super::CPUID;
-#[cfg(any(armv7m, has_fpu, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 use super::CBP;
 use super::SCB;
 
@@ -172,16 +172,16 @@ impl SCB {
             0 => VectActive::ThreadMode,
             2 => VectActive::Exception(Exception::NonMaskableInt),
             3 => VectActive::Exception(Exception::HardFault),
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             4 => VectActive::Exception(Exception::MemoryManagement),
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             5 => VectActive::Exception(Exception::BusFault),
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             6 => VectActive::Exception(Exception::UsageFault),
             #[cfg(any(armv8m, target_arch = "x86_64"))]
             7 => VectActive::Exception(Exception::SecureFault),
             11 => VectActive::Exception(Exception::SVCall),
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             12 => VectActive::Exception(Exception::DebugMonitor),
             14 => VectActive::Exception(Exception::PendSV),
             15 => VectActive::Exception(Exception::SysTick),
@@ -200,15 +200,15 @@ pub enum Exception {
     HardFault,
 
     /// Memory management interrupt (not present on Cortex-M0 variants)
-    #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+    #[cfg(not(armv6m))]
     MemoryManagement,
 
     /// Bus fault interrupt (not present on Cortex-M0 variants)
-    #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+    #[cfg(not(armv6m))]
     BusFault,
 
     /// Usage fault interrupt (not present on Cortex-M0 variants)
-    #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+    #[cfg(not(armv6m))]
     UsageFault,
 
     /// Secure fault interrupt (only on ARMv8-M)
@@ -219,7 +219,7 @@ pub enum Exception {
     SVCall,
 
     /// Debug monitor interrupt (not present on Cortex-M0 variants)
-    #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+    #[cfg(not(armv6m))]
     DebugMonitor,
 
     /// Pend SV interrupt
@@ -237,16 +237,16 @@ impl Exception {
         match *self {
             Exception::NonMaskableInt => -14,
             Exception::HardFault => -13,
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             Exception::MemoryManagement => -12,
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             Exception::BusFault => -11,
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             Exception::UsageFault => -10,
             #[cfg(any(armv8m, target_arch = "x86_64"))]
             Exception::SecureFault => -9,
             Exception::SVCall => -5,
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             Exception::DebugMonitor => -4,
             Exception::PendSV => -2,
             Exception::SysTick => -1,
@@ -277,16 +277,16 @@ impl VectActive {
             0 => VectActive::ThreadMode,
             2 => VectActive::Exception(Exception::NonMaskableInt),
             3 => VectActive::Exception(Exception::HardFault),
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             4 => VectActive::Exception(Exception::MemoryManagement),
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             5 => VectActive::Exception(Exception::BusFault),
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             6 => VectActive::Exception(Exception::UsageFault),
             #[cfg(any(armv8m, target_arch = "x86_64"))]
             7 => VectActive::Exception(Exception::SecureFault),
             11 => VectActive::Exception(Exception::SVCall),
-            #[cfg(any(not(armv6m), target_arch = "x86_64"))]
+            #[cfg(not(armv6m))]
             12 => VectActive::Exception(Exception::DebugMonitor),
             14 => VectActive::Exception(Exception::PendSV),
             15 => VectActive::Exception(Exception::SysTick),
@@ -296,16 +296,16 @@ impl VectActive {
     }
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 mod scb_consts {
     pub const SCB_CCR_IC_MASK: u32 = (1 << 17);
     pub const SCB_CCR_DC_MASK: u32 = (1 << 16);
 }
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 use self::scb_consts::*;
 
-#[cfg(any(armv7m, target_arch = "x86_64"))]
+#[cfg(not(armv6m))]
 impl SCB {
     /// Enables I-Cache if currently disabled
     #[inline]