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| author |  Viktor Sonesten <v@tmplt.dev>
| 2021-04-30 03:00:42 +0200 |
|---|---|---|
| committer | Viktor Sonesten <v@tmplt.dev>
| 2021-04-30 03:00:42 +0200 |
| commit | 9285dccd332e2f14f2dfa7c2eacda652717fc1e0 (patch) | |
| tree | 5021c04166c7163471fdb8bd93d0eff3448bfe6e /src | |
| parent | 930558078e32bff74c101e2f1725f4d94f8c6902 (diff) | |
| download | cortex-m-9285dccd332e2f14f2dfa7c2eacda652717fc1e0.tar.gz cortex-m-9285dccd332e2f14f2dfa7c2eacda652717fc1e0.tar.zst cortex-m-9285dccd332e2f14f2dfa7c2eacda652717fc1e0.zip | |
dcb: add note about vendor-specific trace options
Diffstat (limited to 'src')
| -rw-r--r-- | src/peripheral/dcb.rs | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index 5689cb4..056150b 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -25,6 +25,10 @@ impl DCB { /// `peripheral::DWT` cycle counter to work properly. /// As by STM documentation, this flag is not reset on /// soft-reset, only on power reset. + /// + /// Note: vendor-specific registers may have to be set to completely + /// enable tracing. For example, on the STM32F401RE, `TRACE_MODE` + /// and `TRACE_IOEN` must be configured in `DBGMCU_CR` register. #[inline] pub fn enable_trace(&mut self) { // set bit 24 / TRCENA |