Merge #264

264: Tidy up some inline asm and add compiler fences where appropriate r=therealprof a=adamgreig

This PR updates the inline asm:

* Use compiler-assigned registers instead of specifying r0/r1/r2
* Write multi-line asm as multiple string literals, with normal Rust comments outside the strings
* Add ISB after writing to CONTROL as per ARM architectural requirements (see eg app note 321). As far as I can see no other requirements from AN321 apply here.
* Add compiler fences around enabling and disabling interrupts
    * No runtime barriers are required, but the compiler fences ensure the compiler won't reorder instructions around these operations, which would break critical section soundness.
* Add compiler fences around DMB, DSB, ISB to align compiler behaviour with the barrier runtime behaviour.
* Add compiler fences after the cache enable routines and writing to CONTROL since those routines include an ISB instruction.

Open to feedback on whether more or fewer fences are necessary; I've thought about these a bit but I think it's a tricky subject. I think in general the FFI-esque treatment of the new `asm!` block probably does most of what we need, but I'm told LLVM may still reorder instructions around FFI calls, which we really don't want to happen here.

Co-authored-by: Adam Greig <adam@adamgreig.com>
Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>

0 files changed, 0 insertions, 0 deletions