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| author |  kellerkindt <michael@kellerkindt.com>
| 2018-09-02 15:38:58 +0200 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2018-09-02 15:38:58 +0200 |
| commit | b739654348afde81475493a2431a9f3779f2c7fa (patch) | |
| tree | 094bb577ac05a75488729b75dbcadb6713eb7b89 /src | |
| parent | 3cda015270d38eedaea42301123036fc10cb4a86 (diff) | |
| download | cortex-m-b739654348afde81475493a2431a9f3779f2c7fa.tar.gz cortex-m-b739654348afde81475493a2431a9f3779f2c7fa.tar.zst cortex-m-b739654348afde81475493a2431a9f3779f2c7fa.zip | |
Be more verbose about the bit being set / reset
Diffstat (limited to 'src')
| -rw-r--r-- | src/peripheral/dcb.rs | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index d0202db..5e6014a 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -23,11 +23,13 @@ impl DCB { /// As by STM documentation, this flag is not reset on /// soft-reset, only on power reset. pub fn enable_trace(&mut self) { - unsafe { self.demcr.modify(|w| w | 0x01000000); } + // set bit 24 / TRACENA + unsafe { self.demcr.modify(|w| w | (0x01 << 24)); } } /// Disables TRACE. See `DCB::enable_trace()` for more details pub fn disable_trace(&mut self) { - unsafe { self.demcr.modify(|w| w & !0x01000000); } + // unset bit 24 / TRACENA + unsafe { self.demcr.modify(|w| w & !(0x01 << 24)); } } } |