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| author |  Jorge Aparicio <jorge@japaric.io>
| 2017-06-28 22:26:43 -0500 |
|---|---|---|
| committer | Jorge Aparicio <jorge@japaric.io>
| 2017-06-28 22:29:23 -0500 |
| commit | c0e7dcb9334e735040d7a7e1c3f44cadc61fec73 (patch) | |
| tree | 6dd689cd572580fce6589ff468d2ab89d05a6728 /src | |
| parent | cba4befc6d4c9cf630839a8402330748d82c45e9 (diff) | |
| download | cortex-m-c0e7dcb9334e735040d7a7e1c3f44cadc61fec73.tar.gz cortex-m-c0e7dcb9334e735040d7a7e1c3f44cadc61fec73.tar.zst cortex-m-c0e7dcb9334e735040d7a7e1c3f44cadc61fec73.zip | |
don't expose registers clidr, ctr, ccsidr, csselr to ARMv6-M targets
as these are only available on ARMv7-M devices
closes #46
Diffstat (limited to 'src')
| -rw-r--r-- | src/peripheral/mod.rs | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index 1b21bc5..e210c79 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -104,12 +104,16 @@ pub struct Cpuid { pub isar: [RO<u32>; 5], reserved1: u32, /// Cache Level ID + #[cfg(armv7m)] pub clidr: RO<u32>, /// Cache Type + #[cfg(armv7m)] pub ctr: RO<u32>, /// Cache Size ID + #[cfg(armv7m)] pub ccsidr: RO<u32>, /// Cache Size Selection + #[cfg(armv7m)] pub csselr: RW<u32>, } |